1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 * Ali Saidi
42 */
43
44#include "arch/arm/process.hh"
45
46#include "arch/arm/isa_traits.hh"
47#include "arch/arm/types.hh"
48#include "base/loader/elf_object.hh"
49#include "base/loader/object_file.hh"
50#include "base/logging.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Stack.hh"
53#include "mem/page_table.hh"
54#include "params/Process.hh"
55#include "sim/aux_vector.hh"
56#include "sim/byteswap.hh"
57#include "sim/process_impl.hh"
58#include "sim/syscall_return.hh"
59#include "sim/system.hh"
60
61using namespace std;
62using namespace ArmISA;
63
64ArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile,
65 ObjectFile::Arch _arch)
66 : Process(params, new FuncPageTable(params->name, params->pid, PageBytes),
67 objFile),
68 arch(_arch)
69{
| 1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 * Ali Saidi
42 */
43
44#include "arch/arm/process.hh"
45
46#include "arch/arm/isa_traits.hh"
47#include "arch/arm/types.hh"
48#include "base/loader/elf_object.hh"
49#include "base/loader/object_file.hh"
50#include "base/logging.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Stack.hh"
53#include "mem/page_table.hh"
54#include "params/Process.hh"
55#include "sim/aux_vector.hh"
56#include "sim/byteswap.hh"
57#include "sim/process_impl.hh"
58#include "sim/syscall_return.hh"
59#include "sim/system.hh"
60
61using namespace std;
62using namespace ArmISA;
63
64ArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile,
65 ObjectFile::Arch _arch)
66 : Process(params, new FuncPageTable(params->name, params->pid, PageBytes),
67 objFile),
68 arch(_arch)
69{
|
71}
72
73ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile,
74 ObjectFile::Arch _arch)
75 : ArmProcess(params, objFile, _arch)
76{
77 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
78 objFile->bssSize(), PageBytes);
79 Addr stack_base = 0xbf000000L;
80 Addr max_stack_size = 8 * 1024 * 1024;
81 Addr next_thread_stack_base = stack_base - max_stack_size;
82 Addr mmap_end = 0x40000000L;
83
84 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
85 next_thread_stack_base, mmap_end);
86}
87
88ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile,
89 ObjectFile::Arch _arch)
90 : ArmProcess(params, objFile, _arch)
91{
92 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
93 objFile->bssSize(), PageBytes);
94 Addr stack_base = 0x7fffff0000L;
95 Addr max_stack_size = 8 * 1024 * 1024;
96 Addr next_thread_stack_base = stack_base - max_stack_size;
97 Addr mmap_end = 0x4000000000L;
98
99 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
100 next_thread_stack_base, mmap_end);
101}
102
103void
104ArmProcess32::initState()
105{
106 Process::initState();
107 argsInit<uint32_t>(PageBytes, INTREG_SP);
108 for (int i = 0; i < contextIds.size(); i++) {
109 ThreadContext * tc = system->getThreadContext(contextIds[i]);
110 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
111 // Enable the floating point coprocessors.
112 cpacr.cp10 = 0x3;
113 cpacr.cp11 = 0x3;
114 tc->setMiscReg(MISCREG_CPACR, cpacr);
115 // Generically enable floating point support.
116 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
117 fpexc.en = 1;
118 tc->setMiscReg(MISCREG_FPEXC, fpexc);
119 }
120}
121
122void
123ArmProcess64::initState()
124{
125 Process::initState();
126 argsInit<uint64_t>(PageBytes, INTREG_SP0);
127 for (int i = 0; i < contextIds.size(); i++) {
128 ThreadContext * tc = system->getThreadContext(contextIds[i]);
129 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
130 cpsr.mode = MODE_EL0T;
131 tc->setMiscReg(MISCREG_CPSR, cpsr);
132 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
133 // Enable the floating point coprocessors.
134 cpacr.cp10 = 0x3;
135 cpacr.cp11 = 0x3;
136 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
137 // Generically enable floating point support.
138 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
139 fpexc.en = 1;
140 tc->setMiscReg(MISCREG_FPEXC, fpexc);
141 }
142}
143
144template <class IntType>
145void
146ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
147{
148 int intSize = sizeof(IntType);
149
150 typedef AuxVector<IntType> auxv_t;
151 std::vector<auxv_t> auxv;
152
153 string filename;
154 if (argv.size() < 1)
155 filename = "";
156 else
157 filename = argv[0];
158
159 //We want 16 byte alignment
160 uint64_t align = 16;
161
162 // Patch the ld_bias for dynamic executables.
163 updateBias();
164
165 // load object file into target memory
166 objFile->loadSections(initVirtMem);
167
168 enum ArmCpuFeature {
169 Arm_Swp = 1 << 0,
170 Arm_Half = 1 << 1,
171 Arm_Thumb = 1 << 2,
172 Arm_26Bit = 1 << 3,
173 Arm_FastMult = 1 << 4,
174 Arm_Fpa = 1 << 5,
175 Arm_Vfp = 1 << 6,
176 Arm_Edsp = 1 << 7,
177 Arm_Java = 1 << 8,
178 Arm_Iwmmxt = 1 << 9,
179 Arm_Crunch = 1 << 10,
180 Arm_ThumbEE = 1 << 11,
181 Arm_Neon = 1 << 12,
182 Arm_Vfpv3 = 1 << 13,
183 Arm_Vfpv3d16 = 1 << 14
184 };
185
186 //Setup the auxilliary vectors. These will already have endian conversion.
187 //Auxilliary vectors are loaded only for elf formatted executables.
188 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
189 if (elfObject) {
190
191 if (objFile->getOpSys() == ObjectFile::Linux) {
192 IntType features =
193 Arm_Swp |
194 Arm_Half |
195 Arm_Thumb |
196// Arm_26Bit |
197 Arm_FastMult |
198// Arm_Fpa |
199 Arm_Vfp |
200 Arm_Edsp |
201// Arm_Java |
202// Arm_Iwmmxt |
203// Arm_Crunch |
204 Arm_ThumbEE |
205 Arm_Neon |
206 Arm_Vfpv3 |
207 Arm_Vfpv3d16 |
208 0;
209
210 //Bits which describe the system hardware capabilities
211 //XXX Figure out what these should be
212 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
213 //Frequency at which times() increments
214 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
215 //Whether to enable "secure mode" in the executable
216 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
217 // Pointer to 16 bytes of random data
218 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
219 //The filename of the program
220 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
221 //The string "v71" -- ARM v7 architecture
222 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
223 }
224
225 //The system page size
226 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes));
227 // For statically linked executables, this is the virtual address of the
228 // program header tables if they appear in the executable image
229 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
230 // This is the size of a program header entry from the elf file.
231 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
232 // This is the number of program headers from the original elf file.
233 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
234 // This is the base address of the ELF interpreter; it should be
235 // zero for static executables or contain the base address for
236 // dynamic executables.
237 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
238 //XXX Figure out what this should be.
239 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
240 //The entry point to the program
241 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
242 //Different user and group IDs
243 auxv.push_back(auxv_t(M5_AT_UID, uid()));
244 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
245 auxv.push_back(auxv_t(M5_AT_GID, gid()));
246 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
247 }
248
249 //Figure out how big the initial stack nedes to be
250
251 // A sentry NULL void pointer at the top of the stack.
252 int sentry_size = intSize;
253
254 string platform = "v71";
255 int platform_size = platform.size() + 1;
256
257 // Bytes for AT_RANDOM above, we'll just keep them 0
258 int aux_random_size = 16; // as per the specification
259
260 // The aux vectors are put on the stack in two groups. The first group are
261 // the vectors that are generated as the elf is loaded. The second group
262 // are the ones that were computed ahead of time and include the platform
263 // string.
264 int aux_data_size = filename.size() + 1;
265
266 int env_data_size = 0;
267 for (int i = 0; i < envp.size(); ++i) {
268 env_data_size += envp[i].size() + 1;
269 }
270 int arg_data_size = 0;
271 for (int i = 0; i < argv.size(); ++i) {
272 arg_data_size += argv[i].size() + 1;
273 }
274
275 int info_block_size =
276 sentry_size + env_data_size + arg_data_size +
277 aux_data_size + platform_size + aux_random_size;
278
279 //Each auxilliary vector is two 4 byte words
280 int aux_array_size = intSize * 2 * (auxv.size() + 1);
281
282 int envp_array_size = intSize * (envp.size() + 1);
283 int argv_array_size = intSize * (argv.size() + 1);
284
285 int argc_size = intSize;
286
287 //Figure out the size of the contents of the actual initial frame
288 int frame_size =
289 info_block_size +
290 aux_array_size +
291 envp_array_size +
292 argv_array_size +
293 argc_size;
294
295 //There needs to be padding after the auxiliary vector data so that the
296 //very bottom of the stack is aligned properly.
297 int partial_size = frame_size;
298 int aligned_partial_size = roundUp(partial_size, align);
299 int aux_padding = aligned_partial_size - partial_size;
300
301 int space_needed = frame_size + aux_padding;
302
303 memState->setStackMin(memState->getStackBase() - space_needed);
304 memState->setStackMin(roundDown(memState->getStackMin(), align));
305 memState->setStackSize(memState->getStackBase() - memState->getStackMin());
306
307 // map memory
308 allocateMem(roundDown(memState->getStackMin(), pageSize),
309 roundUp(memState->getStackSize(), pageSize));
310
311 // map out initial stack contents
312 IntType sentry_base = memState->getStackBase() - sentry_size;
313 IntType aux_data_base = sentry_base - aux_data_size;
314 IntType env_data_base = aux_data_base - env_data_size;
315 IntType arg_data_base = env_data_base - arg_data_size;
316 IntType platform_base = arg_data_base - platform_size;
317 IntType aux_random_base = platform_base - aux_random_size;
318 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
319 IntType envp_array_base = auxv_array_base - envp_array_size;
320 IntType argv_array_base = envp_array_base - argv_array_size;
321 IntType argc_base = argv_array_base - argc_size;
322
323 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
324 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
325 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
326 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
327 DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
328 DPRINTF(Stack, "0x%x - platform base\n", platform_base);
329 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
330 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
331 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
332 DPRINTF(Stack, "0x%x - argc \n", argc_base);
333 DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin());
334
335 // write contents to stack
336
337 // figure out argc
338 IntType argc = argv.size();
339 IntType guestArgc = ArmISA::htog(argc);
340
341 //Write out the sentry void *
342 IntType sentry_NULL = 0;
343 initVirtMem.writeBlob(sentry_base,
344 (uint8_t*)&sentry_NULL, sentry_size);
345
346 //Fix up the aux vectors which point to other data
347 for (int i = auxv.size() - 1; i >= 0; i--) {
348 if (auxv[i].a_type == M5_AT_PLATFORM) {
349 auxv[i].a_val = platform_base;
350 initVirtMem.writeString(platform_base, platform.c_str());
351 } else if (auxv[i].a_type == M5_AT_EXECFN) {
352 auxv[i].a_val = aux_data_base;
353 initVirtMem.writeString(aux_data_base, filename.c_str());
354 } else if (auxv[i].a_type == M5_AT_RANDOM) {
355 auxv[i].a_val = aux_random_base;
356 // Just leave the value 0, we don't want randomness
357 }
358 }
359
360 //Copy the aux stuff
361 for (int x = 0; x < auxv.size(); x++) {
362 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
363 (uint8_t*)&(auxv[x].a_type), intSize);
364 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
365 (uint8_t*)&(auxv[x].a_val), intSize);
366 }
367 //Write out the terminating zeroed auxilliary vector
368 const uint64_t zero = 0;
369 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
370 (uint8_t*)&zero, 2 * intSize);
371
372 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
373 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
374
375 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
376
377 ThreadContext *tc = system->getThreadContext(contextIds[0]);
378 //Set the stack pointer register
379 tc->setIntReg(spIndex, memState->getStackMin());
380 //A pointer to a function to run when the program exits. We'll set this
381 //to zero explicitly to make sure this isn't used.
382 tc->setIntReg(ArgumentReg0, 0);
383 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
384 if (argv.size() > 0) {
385 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
386 argv[argv.size() - 1].size() - 1);
387 } else {
388 tc->setIntReg(ArgumentReg1, 0);
389 }
390 if (envp.size() > 0) {
391 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
392 envp[envp.size() - 1].size() - 1);
393 } else {
394 tc->setIntReg(ArgumentReg2, 0);
395 }
396
397 PCState pc;
398 pc.thumb(arch == ObjectFile::Thumb);
399 pc.nextThumb(pc.thumb());
400 pc.aarch64(arch == ObjectFile::Arm64);
401 pc.nextAArch64(pc.aarch64());
402 pc.set(getStartPC() & ~mask(1));
403 tc->pcState(pc);
404
405 //Align the "stackMin" to a page boundary.
406 memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
407}
408
409ArmISA::IntReg
410ArmProcess32::getSyscallArg(ThreadContext *tc, int &i)
411{
412 assert(i < 6);
413 return tc->readIntReg(ArgumentReg0 + i++);
414}
415
416ArmISA::IntReg
417ArmProcess64::getSyscallArg(ThreadContext *tc, int &i)
418{
419 assert(i < 8);
420 return tc->readIntReg(ArgumentReg0 + i++);
421}
422
423ArmISA::IntReg
424ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
425{
426 assert(width == 32 || width == 64);
427 if (width == 32)
428 return getSyscallArg(tc, i);
429
430 // 64 bit arguments are passed starting in an even register
431 if (i % 2 != 0)
432 i++;
433
434 // Registers r0-r6 can be used
435 assert(i < 5);
436 uint64_t val;
437 val = tc->readIntReg(ArgumentReg0 + i++);
438 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
439 return val;
440}
441
442ArmISA::IntReg
443ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
444{
445 return getSyscallArg(tc, i);
446}
447
448
449void
450ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
451{
452 assert(i < 6);
453 tc->setIntReg(ArgumentReg0 + i, val);
454}
455
456void
457ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
458{
459 assert(i < 8);
460 tc->setIntReg(ArgumentReg0 + i, val);
461}
462
463void
464ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
465{
466
467 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
468 // Decode return value
469 if (sysret.encodedValue() >= 0)
470 // FreeBSD checks the carry bit to determine if syscall is succeeded
471 tc->setCCReg(CCREG_C, 0);
472 else {
473 sysret = -sysret.encodedValue();
474 }
475 }
476
477 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
478}
479
480void
481ArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
482{
483
484 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
485 // Decode return value
486 if (sysret.encodedValue() >= 0)
487 // FreeBSD checks the carry bit to determine if syscall is succeeded
488 tc->setCCReg(CCREG_C, 0);
489 else {
490 sysret = -sysret.encodedValue();
491 }
492 }
493
494 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
495}
| 71}
72
73ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile,
74 ObjectFile::Arch _arch)
75 : ArmProcess(params, objFile, _arch)
76{
77 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
78 objFile->bssSize(), PageBytes);
79 Addr stack_base = 0xbf000000L;
80 Addr max_stack_size = 8 * 1024 * 1024;
81 Addr next_thread_stack_base = stack_base - max_stack_size;
82 Addr mmap_end = 0x40000000L;
83
84 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
85 next_thread_stack_base, mmap_end);
86}
87
88ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile,
89 ObjectFile::Arch _arch)
90 : ArmProcess(params, objFile, _arch)
91{
92 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
93 objFile->bssSize(), PageBytes);
94 Addr stack_base = 0x7fffff0000L;
95 Addr max_stack_size = 8 * 1024 * 1024;
96 Addr next_thread_stack_base = stack_base - max_stack_size;
97 Addr mmap_end = 0x4000000000L;
98
99 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
100 next_thread_stack_base, mmap_end);
101}
102
103void
104ArmProcess32::initState()
105{
106 Process::initState();
107 argsInit<uint32_t>(PageBytes, INTREG_SP);
108 for (int i = 0; i < contextIds.size(); i++) {
109 ThreadContext * tc = system->getThreadContext(contextIds[i]);
110 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
111 // Enable the floating point coprocessors.
112 cpacr.cp10 = 0x3;
113 cpacr.cp11 = 0x3;
114 tc->setMiscReg(MISCREG_CPACR, cpacr);
115 // Generically enable floating point support.
116 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
117 fpexc.en = 1;
118 tc->setMiscReg(MISCREG_FPEXC, fpexc);
119 }
120}
121
122void
123ArmProcess64::initState()
124{
125 Process::initState();
126 argsInit<uint64_t>(PageBytes, INTREG_SP0);
127 for (int i = 0; i < contextIds.size(); i++) {
128 ThreadContext * tc = system->getThreadContext(contextIds[i]);
129 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
130 cpsr.mode = MODE_EL0T;
131 tc->setMiscReg(MISCREG_CPSR, cpsr);
132 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
133 // Enable the floating point coprocessors.
134 cpacr.cp10 = 0x3;
135 cpacr.cp11 = 0x3;
136 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
137 // Generically enable floating point support.
138 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
139 fpexc.en = 1;
140 tc->setMiscReg(MISCREG_FPEXC, fpexc);
141 }
142}
143
144template <class IntType>
145void
146ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
147{
148 int intSize = sizeof(IntType);
149
150 typedef AuxVector<IntType> auxv_t;
151 std::vector<auxv_t> auxv;
152
153 string filename;
154 if (argv.size() < 1)
155 filename = "";
156 else
157 filename = argv[0];
158
159 //We want 16 byte alignment
160 uint64_t align = 16;
161
162 // Patch the ld_bias for dynamic executables.
163 updateBias();
164
165 // load object file into target memory
166 objFile->loadSections(initVirtMem);
167
168 enum ArmCpuFeature {
169 Arm_Swp = 1 << 0,
170 Arm_Half = 1 << 1,
171 Arm_Thumb = 1 << 2,
172 Arm_26Bit = 1 << 3,
173 Arm_FastMult = 1 << 4,
174 Arm_Fpa = 1 << 5,
175 Arm_Vfp = 1 << 6,
176 Arm_Edsp = 1 << 7,
177 Arm_Java = 1 << 8,
178 Arm_Iwmmxt = 1 << 9,
179 Arm_Crunch = 1 << 10,
180 Arm_ThumbEE = 1 << 11,
181 Arm_Neon = 1 << 12,
182 Arm_Vfpv3 = 1 << 13,
183 Arm_Vfpv3d16 = 1 << 14
184 };
185
186 //Setup the auxilliary vectors. These will already have endian conversion.
187 //Auxilliary vectors are loaded only for elf formatted executables.
188 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
189 if (elfObject) {
190
191 if (objFile->getOpSys() == ObjectFile::Linux) {
192 IntType features =
193 Arm_Swp |
194 Arm_Half |
195 Arm_Thumb |
196// Arm_26Bit |
197 Arm_FastMult |
198// Arm_Fpa |
199 Arm_Vfp |
200 Arm_Edsp |
201// Arm_Java |
202// Arm_Iwmmxt |
203// Arm_Crunch |
204 Arm_ThumbEE |
205 Arm_Neon |
206 Arm_Vfpv3 |
207 Arm_Vfpv3d16 |
208 0;
209
210 //Bits which describe the system hardware capabilities
211 //XXX Figure out what these should be
212 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
213 //Frequency at which times() increments
214 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
215 //Whether to enable "secure mode" in the executable
216 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
217 // Pointer to 16 bytes of random data
218 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
219 //The filename of the program
220 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
221 //The string "v71" -- ARM v7 architecture
222 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
223 }
224
225 //The system page size
226 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes));
227 // For statically linked executables, this is the virtual address of the
228 // program header tables if they appear in the executable image
229 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
230 // This is the size of a program header entry from the elf file.
231 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
232 // This is the number of program headers from the original elf file.
233 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
234 // This is the base address of the ELF interpreter; it should be
235 // zero for static executables or contain the base address for
236 // dynamic executables.
237 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
238 //XXX Figure out what this should be.
239 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
240 //The entry point to the program
241 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
242 //Different user and group IDs
243 auxv.push_back(auxv_t(M5_AT_UID, uid()));
244 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
245 auxv.push_back(auxv_t(M5_AT_GID, gid()));
246 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
247 }
248
249 //Figure out how big the initial stack nedes to be
250
251 // A sentry NULL void pointer at the top of the stack.
252 int sentry_size = intSize;
253
254 string platform = "v71";
255 int platform_size = platform.size() + 1;
256
257 // Bytes for AT_RANDOM above, we'll just keep them 0
258 int aux_random_size = 16; // as per the specification
259
260 // The aux vectors are put on the stack in two groups. The first group are
261 // the vectors that are generated as the elf is loaded. The second group
262 // are the ones that were computed ahead of time and include the platform
263 // string.
264 int aux_data_size = filename.size() + 1;
265
266 int env_data_size = 0;
267 for (int i = 0; i < envp.size(); ++i) {
268 env_data_size += envp[i].size() + 1;
269 }
270 int arg_data_size = 0;
271 for (int i = 0; i < argv.size(); ++i) {
272 arg_data_size += argv[i].size() + 1;
273 }
274
275 int info_block_size =
276 sentry_size + env_data_size + arg_data_size +
277 aux_data_size + platform_size + aux_random_size;
278
279 //Each auxilliary vector is two 4 byte words
280 int aux_array_size = intSize * 2 * (auxv.size() + 1);
281
282 int envp_array_size = intSize * (envp.size() + 1);
283 int argv_array_size = intSize * (argv.size() + 1);
284
285 int argc_size = intSize;
286
287 //Figure out the size of the contents of the actual initial frame
288 int frame_size =
289 info_block_size +
290 aux_array_size +
291 envp_array_size +
292 argv_array_size +
293 argc_size;
294
295 //There needs to be padding after the auxiliary vector data so that the
296 //very bottom of the stack is aligned properly.
297 int partial_size = frame_size;
298 int aligned_partial_size = roundUp(partial_size, align);
299 int aux_padding = aligned_partial_size - partial_size;
300
301 int space_needed = frame_size + aux_padding;
302
303 memState->setStackMin(memState->getStackBase() - space_needed);
304 memState->setStackMin(roundDown(memState->getStackMin(), align));
305 memState->setStackSize(memState->getStackBase() - memState->getStackMin());
306
307 // map memory
308 allocateMem(roundDown(memState->getStackMin(), pageSize),
309 roundUp(memState->getStackSize(), pageSize));
310
311 // map out initial stack contents
312 IntType sentry_base = memState->getStackBase() - sentry_size;
313 IntType aux_data_base = sentry_base - aux_data_size;
314 IntType env_data_base = aux_data_base - env_data_size;
315 IntType arg_data_base = env_data_base - arg_data_size;
316 IntType platform_base = arg_data_base - platform_size;
317 IntType aux_random_base = platform_base - aux_random_size;
318 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
319 IntType envp_array_base = auxv_array_base - envp_array_size;
320 IntType argv_array_base = envp_array_base - argv_array_size;
321 IntType argc_base = argv_array_base - argc_size;
322
323 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
324 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
325 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
326 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
327 DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
328 DPRINTF(Stack, "0x%x - platform base\n", platform_base);
329 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
330 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
331 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
332 DPRINTF(Stack, "0x%x - argc \n", argc_base);
333 DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin());
334
335 // write contents to stack
336
337 // figure out argc
338 IntType argc = argv.size();
339 IntType guestArgc = ArmISA::htog(argc);
340
341 //Write out the sentry void *
342 IntType sentry_NULL = 0;
343 initVirtMem.writeBlob(sentry_base,
344 (uint8_t*)&sentry_NULL, sentry_size);
345
346 //Fix up the aux vectors which point to other data
347 for (int i = auxv.size() - 1; i >= 0; i--) {
348 if (auxv[i].a_type == M5_AT_PLATFORM) {
349 auxv[i].a_val = platform_base;
350 initVirtMem.writeString(platform_base, platform.c_str());
351 } else if (auxv[i].a_type == M5_AT_EXECFN) {
352 auxv[i].a_val = aux_data_base;
353 initVirtMem.writeString(aux_data_base, filename.c_str());
354 } else if (auxv[i].a_type == M5_AT_RANDOM) {
355 auxv[i].a_val = aux_random_base;
356 // Just leave the value 0, we don't want randomness
357 }
358 }
359
360 //Copy the aux stuff
361 for (int x = 0; x < auxv.size(); x++) {
362 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
363 (uint8_t*)&(auxv[x].a_type), intSize);
364 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
365 (uint8_t*)&(auxv[x].a_val), intSize);
366 }
367 //Write out the terminating zeroed auxilliary vector
368 const uint64_t zero = 0;
369 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
370 (uint8_t*)&zero, 2 * intSize);
371
372 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
373 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
374
375 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
376
377 ThreadContext *tc = system->getThreadContext(contextIds[0]);
378 //Set the stack pointer register
379 tc->setIntReg(spIndex, memState->getStackMin());
380 //A pointer to a function to run when the program exits. We'll set this
381 //to zero explicitly to make sure this isn't used.
382 tc->setIntReg(ArgumentReg0, 0);
383 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
384 if (argv.size() > 0) {
385 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
386 argv[argv.size() - 1].size() - 1);
387 } else {
388 tc->setIntReg(ArgumentReg1, 0);
389 }
390 if (envp.size() > 0) {
391 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
392 envp[envp.size() - 1].size() - 1);
393 } else {
394 tc->setIntReg(ArgumentReg2, 0);
395 }
396
397 PCState pc;
398 pc.thumb(arch == ObjectFile::Thumb);
399 pc.nextThumb(pc.thumb());
400 pc.aarch64(arch == ObjectFile::Arm64);
401 pc.nextAArch64(pc.aarch64());
402 pc.set(getStartPC() & ~mask(1));
403 tc->pcState(pc);
404
405 //Align the "stackMin" to a page boundary.
406 memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
407}
408
409ArmISA::IntReg
410ArmProcess32::getSyscallArg(ThreadContext *tc, int &i)
411{
412 assert(i < 6);
413 return tc->readIntReg(ArgumentReg0 + i++);
414}
415
416ArmISA::IntReg
417ArmProcess64::getSyscallArg(ThreadContext *tc, int &i)
418{
419 assert(i < 8);
420 return tc->readIntReg(ArgumentReg0 + i++);
421}
422
423ArmISA::IntReg
424ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
425{
426 assert(width == 32 || width == 64);
427 if (width == 32)
428 return getSyscallArg(tc, i);
429
430 // 64 bit arguments are passed starting in an even register
431 if (i % 2 != 0)
432 i++;
433
434 // Registers r0-r6 can be used
435 assert(i < 5);
436 uint64_t val;
437 val = tc->readIntReg(ArgumentReg0 + i++);
438 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
439 return val;
440}
441
442ArmISA::IntReg
443ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
444{
445 return getSyscallArg(tc, i);
446}
447
448
449void
450ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
451{
452 assert(i < 6);
453 tc->setIntReg(ArgumentReg0 + i, val);
454}
455
456void
457ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
458{
459 assert(i < 8);
460 tc->setIntReg(ArgumentReg0 + i, val);
461}
462
463void
464ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
465{
466
467 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
468 // Decode return value
469 if (sysret.encodedValue() >= 0)
470 // FreeBSD checks the carry bit to determine if syscall is succeeded
471 tc->setCCReg(CCREG_C, 0);
472 else {
473 sysret = -sysret.encodedValue();
474 }
475 }
476
477 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
478}
479
480void
481ArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
482{
483
484 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
485 // Decode return value
486 if (sysret.encodedValue() >= 0)
487 // FreeBSD checks the carry bit to determine if syscall is succeeded
488 tc->setCCReg(CCREG_C, 0);
489 else {
490 sysret = -sysret.encodedValue();
491 }
492 }
493
494 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
495}
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