1/* 2 * Copyright (c) 2010, 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 * Ali Saidi 42 */ 43 44#include "arch/arm/process.hh" 45 46#include "arch/arm/isa_traits.hh" 47#include "arch/arm/types.hh" 48#include "base/loader/elf_object.hh" 49#include "base/loader/object_file.hh" 50#include "base/logging.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Stack.hh" 53#include "mem/page_table.hh" 54#include "params/Process.hh" 55#include "sim/aux_vector.hh" 56#include "sim/byteswap.hh" 57#include "sim/process_impl.hh" 58#include "sim/syscall_return.hh" 59#include "sim/system.hh" 60 61using namespace std; 62using namespace ArmISA; 63 64ArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile, 65 ObjectFile::Arch _arch)
| 1/* 2 * Copyright (c) 2010, 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 * Ali Saidi 42 */ 43 44#include "arch/arm/process.hh" 45 46#include "arch/arm/isa_traits.hh" 47#include "arch/arm/types.hh" 48#include "base/loader/elf_object.hh" 49#include "base/loader/object_file.hh" 50#include "base/logging.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Stack.hh" 53#include "mem/page_table.hh" 54#include "params/Process.hh" 55#include "sim/aux_vector.hh" 56#include "sim/byteswap.hh" 57#include "sim/process_impl.hh" 58#include "sim/syscall_return.hh" 59#include "sim/system.hh" 60 61using namespace std; 62using namespace ArmISA; 63 64ArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile, 65 ObjectFile::Arch _arch)
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67 arch(_arch) 68{ 69 fatal_if(!params->useArchPT, "Arch page tables not implemented."); 70} 71 72ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile, 73 ObjectFile::Arch _arch) 74 : ArmProcess(params, objFile, _arch) 75{ 76 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 77 objFile->bssSize(), PageBytes); 78 Addr stack_base = 0xbf000000L; 79 Addr max_stack_size = 8 * 1024 * 1024; 80 Addr next_thread_stack_base = stack_base - max_stack_size; 81 Addr mmap_end = 0x40000000L; 82 83 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 84 next_thread_stack_base, mmap_end); 85} 86 87ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile, 88 ObjectFile::Arch _arch) 89 : ArmProcess(params, objFile, _arch) 90{ 91 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 92 objFile->bssSize(), PageBytes); 93 Addr stack_base = 0x7fffff0000L; 94 Addr max_stack_size = 8 * 1024 * 1024; 95 Addr next_thread_stack_base = stack_base - max_stack_size; 96 Addr mmap_end = 0x4000000000L; 97 98 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 99 next_thread_stack_base, mmap_end); 100} 101 102void 103ArmProcess32::initState() 104{ 105 Process::initState(); 106 argsInit<uint32_t>(PageBytes, INTREG_SP); 107 for (int i = 0; i < contextIds.size(); i++) { 108 ThreadContext * tc = system->getThreadContext(contextIds[i]); 109 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); 110 // Enable the floating point coprocessors. 111 cpacr.cp10 = 0x3; 112 cpacr.cp11 = 0x3; 113 tc->setMiscReg(MISCREG_CPACR, cpacr); 114 // Generically enable floating point support. 115 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 116 fpexc.en = 1; 117 tc->setMiscReg(MISCREG_FPEXC, fpexc); 118 } 119} 120 121void 122ArmProcess64::initState() 123{ 124 Process::initState(); 125 argsInit<uint64_t>(PageBytes, INTREG_SP0); 126 for (int i = 0; i < contextIds.size(); i++) { 127 ThreadContext * tc = system->getThreadContext(contextIds[i]); 128 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 129 cpsr.mode = MODE_EL0T; 130 tc->setMiscReg(MISCREG_CPSR, cpsr); 131 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); 132 // Enable the floating point coprocessors. 133 cpacr.cp10 = 0x3; 134 cpacr.cp11 = 0x3; 135 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr); 136 // Generically enable floating point support. 137 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 138 fpexc.en = 1; 139 tc->setMiscReg(MISCREG_FPEXC, fpexc); 140 } 141} 142 143template <class IntType> 144void 145ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) 146{ 147 int intSize = sizeof(IntType); 148 149 typedef AuxVector<IntType> auxv_t; 150 std::vector<auxv_t> auxv; 151 152 string filename; 153 if (argv.size() < 1) 154 filename = ""; 155 else 156 filename = argv[0]; 157 158 //We want 16 byte alignment 159 uint64_t align = 16; 160 161 // Patch the ld_bias for dynamic executables. 162 updateBias(); 163 164 // load object file into target memory 165 objFile->loadSections(initVirtMem); 166 167 enum ArmCpuFeature { 168 Arm_Swp = 1 << 0, 169 Arm_Half = 1 << 1, 170 Arm_Thumb = 1 << 2, 171 Arm_26Bit = 1 << 3, 172 Arm_FastMult = 1 << 4, 173 Arm_Fpa = 1 << 5, 174 Arm_Vfp = 1 << 6, 175 Arm_Edsp = 1 << 7, 176 Arm_Java = 1 << 8, 177 Arm_Iwmmxt = 1 << 9, 178 Arm_Crunch = 1 << 10, 179 Arm_ThumbEE = 1 << 11, 180 Arm_Neon = 1 << 12, 181 Arm_Vfpv3 = 1 << 13, 182 Arm_Vfpv3d16 = 1 << 14 183 }; 184 185 //Setup the auxilliary vectors. These will already have endian conversion. 186 //Auxilliary vectors are loaded only for elf formatted executables. 187 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 188 if (elfObject) { 189 190 if (objFile->getOpSys() == ObjectFile::Linux) { 191 IntType features = 192 Arm_Swp | 193 Arm_Half | 194 Arm_Thumb | 195// Arm_26Bit | 196 Arm_FastMult | 197// Arm_Fpa | 198 Arm_Vfp | 199 Arm_Edsp | 200// Arm_Java | 201// Arm_Iwmmxt | 202// Arm_Crunch | 203 Arm_ThumbEE | 204 Arm_Neon | 205 Arm_Vfpv3 | 206 Arm_Vfpv3d16 | 207 0; 208 209 //Bits which describe the system hardware capabilities 210 //XXX Figure out what these should be 211 auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 212 //Frequency at which times() increments 213 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64)); 214 //Whether to enable "secure mode" in the executable 215 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 216 // Pointer to 16 bytes of random data 217 auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 218 //The filename of the program 219 auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 220 //The string "v71" -- ARM v7 architecture 221 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 222 } 223 224 //The system page size 225 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes)); 226 // For statically linked executables, this is the virtual address of the 227 // program header tables if they appear in the executable image 228 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 229 // This is the size of a program header entry from the elf file. 230 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 231 // This is the number of program headers from the original elf file. 232 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 233 // This is the base address of the ELF interpreter; it should be 234 // zero for static executables or contain the base address for 235 // dynamic executables. 236 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 237 //XXX Figure out what this should be. 238 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 239 //The entry point to the program 240 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 241 //Different user and group IDs 242 auxv.push_back(auxv_t(M5_AT_UID, uid())); 243 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 244 auxv.push_back(auxv_t(M5_AT_GID, gid())); 245 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 246 } 247 248 //Figure out how big the initial stack nedes to be 249 250 // A sentry NULL void pointer at the top of the stack. 251 int sentry_size = intSize; 252 253 string platform = "v71"; 254 int platform_size = platform.size() + 1; 255 256 // Bytes for AT_RANDOM above, we'll just keep them 0 257 int aux_random_size = 16; // as per the specification 258 259 // The aux vectors are put on the stack in two groups. The first group are 260 // the vectors that are generated as the elf is loaded. The second group 261 // are the ones that were computed ahead of time and include the platform 262 // string. 263 int aux_data_size = filename.size() + 1; 264 265 int env_data_size = 0; 266 for (int i = 0; i < envp.size(); ++i) { 267 env_data_size += envp[i].size() + 1; 268 } 269 int arg_data_size = 0; 270 for (int i = 0; i < argv.size(); ++i) { 271 arg_data_size += argv[i].size() + 1; 272 } 273 274 int info_block_size = 275 sentry_size + env_data_size + arg_data_size + 276 aux_data_size + platform_size + aux_random_size; 277 278 //Each auxilliary vector is two 4 byte words 279 int aux_array_size = intSize * 2 * (auxv.size() + 1); 280 281 int envp_array_size = intSize * (envp.size() + 1); 282 int argv_array_size = intSize * (argv.size() + 1); 283 284 int argc_size = intSize; 285 286 //Figure out the size of the contents of the actual initial frame 287 int frame_size = 288 info_block_size + 289 aux_array_size + 290 envp_array_size + 291 argv_array_size + 292 argc_size; 293 294 //There needs to be padding after the auxiliary vector data so that the 295 //very bottom of the stack is aligned properly. 296 int partial_size = frame_size; 297 int aligned_partial_size = roundUp(partial_size, align); 298 int aux_padding = aligned_partial_size - partial_size; 299 300 int space_needed = frame_size + aux_padding; 301 302 memState->setStackMin(memState->getStackBase() - space_needed); 303 memState->setStackMin(roundDown(memState->getStackMin(), align)); 304 memState->setStackSize(memState->getStackBase() - memState->getStackMin()); 305 306 // map memory 307 allocateMem(roundDown(memState->getStackMin(), pageSize), 308 roundUp(memState->getStackSize(), pageSize)); 309 310 // map out initial stack contents 311 IntType sentry_base = memState->getStackBase() - sentry_size; 312 IntType aux_data_base = sentry_base - aux_data_size; 313 IntType env_data_base = aux_data_base - env_data_size; 314 IntType arg_data_base = env_data_base - arg_data_size; 315 IntType platform_base = arg_data_base - platform_size; 316 IntType aux_random_base = platform_base - aux_random_size; 317 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding; 318 IntType envp_array_base = auxv_array_base - envp_array_size; 319 IntType argv_array_base = envp_array_base - argv_array_size; 320 IntType argc_base = argv_array_base - argc_size; 321 322 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 323 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 324 DPRINTF(Stack, "0x%x - env data\n", env_data_base); 325 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 326 DPRINTF(Stack, "0x%x - random data\n", aux_random_base); 327 DPRINTF(Stack, "0x%x - platform base\n", platform_base); 328 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 329 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 330 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 331 DPRINTF(Stack, "0x%x - argc \n", argc_base); 332 DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin()); 333 334 // write contents to stack 335 336 // figure out argc 337 IntType argc = argv.size(); 338 IntType guestArgc = ArmISA::htog(argc); 339 340 //Write out the sentry void * 341 IntType sentry_NULL = 0; 342 initVirtMem.writeBlob(sentry_base, 343 (uint8_t*)&sentry_NULL, sentry_size); 344 345 //Fix up the aux vectors which point to other data 346 for (int i = auxv.size() - 1; i >= 0; i--) { 347 if (auxv[i].a_type == M5_AT_PLATFORM) { 348 auxv[i].a_val = platform_base; 349 initVirtMem.writeString(platform_base, platform.c_str()); 350 } else if (auxv[i].a_type == M5_AT_EXECFN) { 351 auxv[i].a_val = aux_data_base; 352 initVirtMem.writeString(aux_data_base, filename.c_str()); 353 } else if (auxv[i].a_type == M5_AT_RANDOM) { 354 auxv[i].a_val = aux_random_base; 355 // Just leave the value 0, we don't want randomness 356 } 357 } 358 359 //Copy the aux stuff 360 for (int x = 0; x < auxv.size(); x++) { 361 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 362 (uint8_t*)&(auxv[x].a_type), intSize); 363 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 364 (uint8_t*)&(auxv[x].a_val), intSize); 365 } 366 //Write out the terminating zeroed auxilliary vector 367 const uint64_t zero = 0; 368 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(), 369 (uint8_t*)&zero, 2 * intSize); 370 371 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 372 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 373 374 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 375 376 ThreadContext *tc = system->getThreadContext(contextIds[0]); 377 //Set the stack pointer register 378 tc->setIntReg(spIndex, memState->getStackMin()); 379 //A pointer to a function to run when the program exits. We'll set this 380 //to zero explicitly to make sure this isn't used. 381 tc->setIntReg(ArgumentReg0, 0); 382 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively 383 if (argv.size() > 0) { 384 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size - 385 argv[argv.size() - 1].size() - 1); 386 } else { 387 tc->setIntReg(ArgumentReg1, 0); 388 } 389 if (envp.size() > 0) { 390 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size - 391 envp[envp.size() - 1].size() - 1); 392 } else { 393 tc->setIntReg(ArgumentReg2, 0); 394 } 395 396 PCState pc; 397 pc.thumb(arch == ObjectFile::Thumb); 398 pc.nextThumb(pc.thumb()); 399 pc.aarch64(arch == ObjectFile::Arm64); 400 pc.nextAArch64(pc.aarch64()); 401 pc.set(getStartPC() & ~mask(1)); 402 tc->pcState(pc); 403 404 //Align the "stackMin" to a page boundary. 405 memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 406} 407 408ArmISA::IntReg 409ArmProcess32::getSyscallArg(ThreadContext *tc, int &i) 410{ 411 assert(i < 6); 412 return tc->readIntReg(ArgumentReg0 + i++); 413} 414 415ArmISA::IntReg 416ArmProcess64::getSyscallArg(ThreadContext *tc, int &i) 417{ 418 assert(i < 8); 419 return tc->readIntReg(ArgumentReg0 + i++); 420} 421 422ArmISA::IntReg 423ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width) 424{ 425 assert(width == 32 || width == 64); 426 if (width == 32) 427 return getSyscallArg(tc, i); 428 429 // 64 bit arguments are passed starting in an even register 430 if (i % 2 != 0) 431 i++; 432 433 // Registers r0-r6 can be used 434 assert(i < 5); 435 uint64_t val; 436 val = tc->readIntReg(ArgumentReg0 + i++); 437 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32); 438 return val; 439} 440 441ArmISA::IntReg 442ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width) 443{ 444 return getSyscallArg(tc, i); 445} 446 447 448void 449ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 450{ 451 assert(i < 6); 452 tc->setIntReg(ArgumentReg0 + i, val); 453} 454 455void 456ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 457{ 458 assert(i < 8); 459 tc->setIntReg(ArgumentReg0 + i, val); 460} 461 462void 463ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 464{ 465 466 if (objFile->getOpSys() == ObjectFile::FreeBSD) { 467 // Decode return value 468 if (sysret.encodedValue() >= 0) 469 // FreeBSD checks the carry bit to determine if syscall is succeeded 470 tc->setCCReg(CCREG_C, 0); 471 else { 472 sysret = -sysret.encodedValue(); 473 } 474 } 475 476 tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 477} 478 479void 480ArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 481{ 482 483 if (objFile->getOpSys() == ObjectFile::FreeBSD) { 484 // Decode return value 485 if (sysret.encodedValue() >= 0) 486 // FreeBSD checks the carry bit to determine if syscall is succeeded 487 tc->setCCReg(CCREG_C, 0); 488 else { 489 sysret = -sysret.encodedValue(); 490 } 491 } 492 493 tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 494}
| 68 arch(_arch) 69{ 70 fatal_if(!params->useArchPT, "Arch page tables not implemented."); 71} 72 73ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile, 74 ObjectFile::Arch _arch) 75 : ArmProcess(params, objFile, _arch) 76{ 77 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 78 objFile->bssSize(), PageBytes); 79 Addr stack_base = 0xbf000000L; 80 Addr max_stack_size = 8 * 1024 * 1024; 81 Addr next_thread_stack_base = stack_base - max_stack_size; 82 Addr mmap_end = 0x40000000L; 83 84 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 85 next_thread_stack_base, mmap_end); 86} 87 88ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile, 89 ObjectFile::Arch _arch) 90 : ArmProcess(params, objFile, _arch) 91{ 92 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 93 objFile->bssSize(), PageBytes); 94 Addr stack_base = 0x7fffff0000L; 95 Addr max_stack_size = 8 * 1024 * 1024; 96 Addr next_thread_stack_base = stack_base - max_stack_size; 97 Addr mmap_end = 0x4000000000L; 98 99 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 100 next_thread_stack_base, mmap_end); 101} 102 103void 104ArmProcess32::initState() 105{ 106 Process::initState(); 107 argsInit<uint32_t>(PageBytes, INTREG_SP); 108 for (int i = 0; i < contextIds.size(); i++) { 109 ThreadContext * tc = system->getThreadContext(contextIds[i]); 110 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); 111 // Enable the floating point coprocessors. 112 cpacr.cp10 = 0x3; 113 cpacr.cp11 = 0x3; 114 tc->setMiscReg(MISCREG_CPACR, cpacr); 115 // Generically enable floating point support. 116 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 117 fpexc.en = 1; 118 tc->setMiscReg(MISCREG_FPEXC, fpexc); 119 } 120} 121 122void 123ArmProcess64::initState() 124{ 125 Process::initState(); 126 argsInit<uint64_t>(PageBytes, INTREG_SP0); 127 for (int i = 0; i < contextIds.size(); i++) { 128 ThreadContext * tc = system->getThreadContext(contextIds[i]); 129 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 130 cpsr.mode = MODE_EL0T; 131 tc->setMiscReg(MISCREG_CPSR, cpsr); 132 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); 133 // Enable the floating point coprocessors. 134 cpacr.cp10 = 0x3; 135 cpacr.cp11 = 0x3; 136 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr); 137 // Generically enable floating point support. 138 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 139 fpexc.en = 1; 140 tc->setMiscReg(MISCREG_FPEXC, fpexc); 141 } 142} 143 144template <class IntType> 145void 146ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) 147{ 148 int intSize = sizeof(IntType); 149 150 typedef AuxVector<IntType> auxv_t; 151 std::vector<auxv_t> auxv; 152 153 string filename; 154 if (argv.size() < 1) 155 filename = ""; 156 else 157 filename = argv[0]; 158 159 //We want 16 byte alignment 160 uint64_t align = 16; 161 162 // Patch the ld_bias for dynamic executables. 163 updateBias(); 164 165 // load object file into target memory 166 objFile->loadSections(initVirtMem); 167 168 enum ArmCpuFeature { 169 Arm_Swp = 1 << 0, 170 Arm_Half = 1 << 1, 171 Arm_Thumb = 1 << 2, 172 Arm_26Bit = 1 << 3, 173 Arm_FastMult = 1 << 4, 174 Arm_Fpa = 1 << 5, 175 Arm_Vfp = 1 << 6, 176 Arm_Edsp = 1 << 7, 177 Arm_Java = 1 << 8, 178 Arm_Iwmmxt = 1 << 9, 179 Arm_Crunch = 1 << 10, 180 Arm_ThumbEE = 1 << 11, 181 Arm_Neon = 1 << 12, 182 Arm_Vfpv3 = 1 << 13, 183 Arm_Vfpv3d16 = 1 << 14 184 }; 185 186 //Setup the auxilliary vectors. These will already have endian conversion. 187 //Auxilliary vectors are loaded only for elf formatted executables. 188 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 189 if (elfObject) { 190 191 if (objFile->getOpSys() == ObjectFile::Linux) { 192 IntType features = 193 Arm_Swp | 194 Arm_Half | 195 Arm_Thumb | 196// Arm_26Bit | 197 Arm_FastMult | 198// Arm_Fpa | 199 Arm_Vfp | 200 Arm_Edsp | 201// Arm_Java | 202// Arm_Iwmmxt | 203// Arm_Crunch | 204 Arm_ThumbEE | 205 Arm_Neon | 206 Arm_Vfpv3 | 207 Arm_Vfpv3d16 | 208 0; 209 210 //Bits which describe the system hardware capabilities 211 //XXX Figure out what these should be 212 auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 213 //Frequency at which times() increments 214 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64)); 215 //Whether to enable "secure mode" in the executable 216 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 217 // Pointer to 16 bytes of random data 218 auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 219 //The filename of the program 220 auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 221 //The string "v71" -- ARM v7 architecture 222 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 223 } 224 225 //The system page size 226 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes)); 227 // For statically linked executables, this is the virtual address of the 228 // program header tables if they appear in the executable image 229 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 230 // This is the size of a program header entry from the elf file. 231 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 232 // This is the number of program headers from the original elf file. 233 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 234 // This is the base address of the ELF interpreter; it should be 235 // zero for static executables or contain the base address for 236 // dynamic executables. 237 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 238 //XXX Figure out what this should be. 239 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 240 //The entry point to the program 241 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 242 //Different user and group IDs 243 auxv.push_back(auxv_t(M5_AT_UID, uid())); 244 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 245 auxv.push_back(auxv_t(M5_AT_GID, gid())); 246 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 247 } 248 249 //Figure out how big the initial stack nedes to be 250 251 // A sentry NULL void pointer at the top of the stack. 252 int sentry_size = intSize; 253 254 string platform = "v71"; 255 int platform_size = platform.size() + 1; 256 257 // Bytes for AT_RANDOM above, we'll just keep them 0 258 int aux_random_size = 16; // as per the specification 259 260 // The aux vectors are put on the stack in two groups. The first group are 261 // the vectors that are generated as the elf is loaded. The second group 262 // are the ones that were computed ahead of time and include the platform 263 // string. 264 int aux_data_size = filename.size() + 1; 265 266 int env_data_size = 0; 267 for (int i = 0; i < envp.size(); ++i) { 268 env_data_size += envp[i].size() + 1; 269 } 270 int arg_data_size = 0; 271 for (int i = 0; i < argv.size(); ++i) { 272 arg_data_size += argv[i].size() + 1; 273 } 274 275 int info_block_size = 276 sentry_size + env_data_size + arg_data_size + 277 aux_data_size + platform_size + aux_random_size; 278 279 //Each auxilliary vector is two 4 byte words 280 int aux_array_size = intSize * 2 * (auxv.size() + 1); 281 282 int envp_array_size = intSize * (envp.size() + 1); 283 int argv_array_size = intSize * (argv.size() + 1); 284 285 int argc_size = intSize; 286 287 //Figure out the size of the contents of the actual initial frame 288 int frame_size = 289 info_block_size + 290 aux_array_size + 291 envp_array_size + 292 argv_array_size + 293 argc_size; 294 295 //There needs to be padding after the auxiliary vector data so that the 296 //very bottom of the stack is aligned properly. 297 int partial_size = frame_size; 298 int aligned_partial_size = roundUp(partial_size, align); 299 int aux_padding = aligned_partial_size - partial_size; 300 301 int space_needed = frame_size + aux_padding; 302 303 memState->setStackMin(memState->getStackBase() - space_needed); 304 memState->setStackMin(roundDown(memState->getStackMin(), align)); 305 memState->setStackSize(memState->getStackBase() - memState->getStackMin()); 306 307 // map memory 308 allocateMem(roundDown(memState->getStackMin(), pageSize), 309 roundUp(memState->getStackSize(), pageSize)); 310 311 // map out initial stack contents 312 IntType sentry_base = memState->getStackBase() - sentry_size; 313 IntType aux_data_base = sentry_base - aux_data_size; 314 IntType env_data_base = aux_data_base - env_data_size; 315 IntType arg_data_base = env_data_base - arg_data_size; 316 IntType platform_base = arg_data_base - platform_size; 317 IntType aux_random_base = platform_base - aux_random_size; 318 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding; 319 IntType envp_array_base = auxv_array_base - envp_array_size; 320 IntType argv_array_base = envp_array_base - argv_array_size; 321 IntType argc_base = argv_array_base - argc_size; 322 323 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 324 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 325 DPRINTF(Stack, "0x%x - env data\n", env_data_base); 326 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 327 DPRINTF(Stack, "0x%x - random data\n", aux_random_base); 328 DPRINTF(Stack, "0x%x - platform base\n", platform_base); 329 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 330 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 331 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 332 DPRINTF(Stack, "0x%x - argc \n", argc_base); 333 DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin()); 334 335 // write contents to stack 336 337 // figure out argc 338 IntType argc = argv.size(); 339 IntType guestArgc = ArmISA::htog(argc); 340 341 //Write out the sentry void * 342 IntType sentry_NULL = 0; 343 initVirtMem.writeBlob(sentry_base, 344 (uint8_t*)&sentry_NULL, sentry_size); 345 346 //Fix up the aux vectors which point to other data 347 for (int i = auxv.size() - 1; i >= 0; i--) { 348 if (auxv[i].a_type == M5_AT_PLATFORM) { 349 auxv[i].a_val = platform_base; 350 initVirtMem.writeString(platform_base, platform.c_str()); 351 } else if (auxv[i].a_type == M5_AT_EXECFN) { 352 auxv[i].a_val = aux_data_base; 353 initVirtMem.writeString(aux_data_base, filename.c_str()); 354 } else if (auxv[i].a_type == M5_AT_RANDOM) { 355 auxv[i].a_val = aux_random_base; 356 // Just leave the value 0, we don't want randomness 357 } 358 } 359 360 //Copy the aux stuff 361 for (int x = 0; x < auxv.size(); x++) { 362 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 363 (uint8_t*)&(auxv[x].a_type), intSize); 364 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 365 (uint8_t*)&(auxv[x].a_val), intSize); 366 } 367 //Write out the terminating zeroed auxilliary vector 368 const uint64_t zero = 0; 369 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(), 370 (uint8_t*)&zero, 2 * intSize); 371 372 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 373 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 374 375 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 376 377 ThreadContext *tc = system->getThreadContext(contextIds[0]); 378 //Set the stack pointer register 379 tc->setIntReg(spIndex, memState->getStackMin()); 380 //A pointer to a function to run when the program exits. We'll set this 381 //to zero explicitly to make sure this isn't used. 382 tc->setIntReg(ArgumentReg0, 0); 383 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively 384 if (argv.size() > 0) { 385 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size - 386 argv[argv.size() - 1].size() - 1); 387 } else { 388 tc->setIntReg(ArgumentReg1, 0); 389 } 390 if (envp.size() > 0) { 391 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size - 392 envp[envp.size() - 1].size() - 1); 393 } else { 394 tc->setIntReg(ArgumentReg2, 0); 395 } 396 397 PCState pc; 398 pc.thumb(arch == ObjectFile::Thumb); 399 pc.nextThumb(pc.thumb()); 400 pc.aarch64(arch == ObjectFile::Arm64); 401 pc.nextAArch64(pc.aarch64()); 402 pc.set(getStartPC() & ~mask(1)); 403 tc->pcState(pc); 404 405 //Align the "stackMin" to a page boundary. 406 memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 407} 408 409ArmISA::IntReg 410ArmProcess32::getSyscallArg(ThreadContext *tc, int &i) 411{ 412 assert(i < 6); 413 return tc->readIntReg(ArgumentReg0 + i++); 414} 415 416ArmISA::IntReg 417ArmProcess64::getSyscallArg(ThreadContext *tc, int &i) 418{ 419 assert(i < 8); 420 return tc->readIntReg(ArgumentReg0 + i++); 421} 422 423ArmISA::IntReg 424ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width) 425{ 426 assert(width == 32 || width == 64); 427 if (width == 32) 428 return getSyscallArg(tc, i); 429 430 // 64 bit arguments are passed starting in an even register 431 if (i % 2 != 0) 432 i++; 433 434 // Registers r0-r6 can be used 435 assert(i < 5); 436 uint64_t val; 437 val = tc->readIntReg(ArgumentReg0 + i++); 438 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32); 439 return val; 440} 441 442ArmISA::IntReg 443ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width) 444{ 445 return getSyscallArg(tc, i); 446} 447 448 449void 450ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 451{ 452 assert(i < 6); 453 tc->setIntReg(ArgumentReg0 + i, val); 454} 455 456void 457ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 458{ 459 assert(i < 8); 460 tc->setIntReg(ArgumentReg0 + i, val); 461} 462 463void 464ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 465{ 466 467 if (objFile->getOpSys() == ObjectFile::FreeBSD) { 468 // Decode return value 469 if (sysret.encodedValue() >= 0) 470 // FreeBSD checks the carry bit to determine if syscall is succeeded 471 tc->setCCReg(CCREG_C, 0); 472 else { 473 sysret = -sysret.encodedValue(); 474 } 475 } 476 477 tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 478} 479 480void 481ArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 482{ 483 484 if (objFile->getOpSys() == ObjectFile::FreeBSD) { 485 // Decode return value 486 if (sysret.encodedValue() >= 0) 487 // FreeBSD checks the carry bit to determine if syscall is succeeded 488 tc->setCCReg(CCREG_C, 0); 489 else { 490 sysret = -sysret.encodedValue(); 491 } 492 } 493 494 tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 495}
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