1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 * Ali Saidi
42 */
43
44#include "arch/arm/process.hh"
45
46#include "arch/arm/isa_traits.hh"
47#include "arch/arm/types.hh"
48#include "base/loader/elf_object.hh"
49#include "base/loader/object_file.hh"
50#include "base/misc.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Stack.hh"
53#include "mem/page_table.hh"
54#include "sim/byteswap.hh"
55#include "sim/process_impl.hh"
56#include "sim/syscall_return.hh"
57#include "sim/system.hh"
58
59using namespace std;
60using namespace ArmISA;
61
| 1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 * Ali Saidi
42 */
43
44#include "arch/arm/process.hh"
45
46#include "arch/arm/isa_traits.hh"
47#include "arch/arm/types.hh"
48#include "base/loader/elf_object.hh"
49#include "base/loader/object_file.hh"
50#include "base/misc.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Stack.hh"
53#include "mem/page_table.hh"
54#include "sim/byteswap.hh"
55#include "sim/process_impl.hh"
56#include "sim/syscall_return.hh"
57#include "sim/system.hh"
58
59using namespace std;
60using namespace ArmISA;
61
|
62ArmLiveProcess::ArmLiveProcess(LiveProcessParams *params, ObjectFile *objFile,
63 ObjectFile::Arch _arch)
64 : LiveProcess(params, objFile), arch(_arch)
| 62ArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile,
63 ObjectFile::Arch _arch)
64 : Process(params, objFile), arch(_arch)
|
65{
66}
67
| 65{
66}
67
|
68ArmLiveProcess32::ArmLiveProcess32(LiveProcessParams *params,
69 ObjectFile *objFile, ObjectFile::Arch _arch)
70 : ArmLiveProcess(params, objFile, _arch)
| 68ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile,
69 ObjectFile::Arch _arch)
70 : ArmProcess(params, objFile, _arch)
|
71{
72 stack_base = 0xbf000000L;
73
74 // Set pointer for next thread stack. Reserve 8M for main stack.
75 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
76
77 // Set up break point (Top of Heap)
78 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
79 brk_point = roundUp(brk_point, PageBytes);
80
81 // Set up region for mmaps. For now, start at bottom of kuseg space.
82 mmap_end = 0x40000000L;
83}
84
| 71{
72 stack_base = 0xbf000000L;
73
74 // Set pointer for next thread stack. Reserve 8M for main stack.
75 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
76
77 // Set up break point (Top of Heap)
78 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
79 brk_point = roundUp(brk_point, PageBytes);
80
81 // Set up region for mmaps. For now, start at bottom of kuseg space.
82 mmap_end = 0x40000000L;
83}
84
|
85ArmLiveProcess64::ArmLiveProcess64(LiveProcessParams *params,
86 ObjectFile *objFile, ObjectFile::Arch _arch)
87 : ArmLiveProcess(params, objFile, _arch)
| 85ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile,
86 ObjectFile::Arch _arch)
87 : ArmProcess(params, objFile, _arch)
|
88{
89 stack_base = 0x7fffff0000L;
90
91 // Set pointer for next thread stack. Reserve 8M for main stack.
92 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
93
94 // Set up break point (Top of Heap)
95 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
96 brk_point = roundUp(brk_point, PageBytes);
97
98 // Set up region for mmaps. For now, start at bottom of kuseg space.
99 mmap_end = 0x4000000000L;
100}
101
102void
| 88{
89 stack_base = 0x7fffff0000L;
90
91 // Set pointer for next thread stack. Reserve 8M for main stack.
92 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
93
94 // Set up break point (Top of Heap)
95 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
96 brk_point = roundUp(brk_point, PageBytes);
97
98 // Set up region for mmaps. For now, start at bottom of kuseg space.
99 mmap_end = 0x4000000000L;
100}
101
102void
|
103ArmLiveProcess32::initState()
| 103ArmProcess32::initState()
|
104{
| 104{
|
105 LiveProcess::initState();
| 105 Process::initState();
|
106 argsInit<uint32_t>(PageBytes, INTREG_SP);
107 for (int i = 0; i < contextIds.size(); i++) {
108 ThreadContext * tc = system->getThreadContext(contextIds[i]);
109 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
110 // Enable the floating point coprocessors.
111 cpacr.cp10 = 0x3;
112 cpacr.cp11 = 0x3;
113 tc->setMiscReg(MISCREG_CPACR, cpacr);
114 // Generically enable floating point support.
115 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
116 fpexc.en = 1;
117 tc->setMiscReg(MISCREG_FPEXC, fpexc);
118 }
119}
120
121void
| 106 argsInit<uint32_t>(PageBytes, INTREG_SP);
107 for (int i = 0; i < contextIds.size(); i++) {
108 ThreadContext * tc = system->getThreadContext(contextIds[i]);
109 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
110 // Enable the floating point coprocessors.
111 cpacr.cp10 = 0x3;
112 cpacr.cp11 = 0x3;
113 tc->setMiscReg(MISCREG_CPACR, cpacr);
114 // Generically enable floating point support.
115 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
116 fpexc.en = 1;
117 tc->setMiscReg(MISCREG_FPEXC, fpexc);
118 }
119}
120
121void
|
122ArmLiveProcess64::initState()
| 122ArmProcess64::initState()
|
123{
| 123{
|
124 LiveProcess::initState();
| 124 Process::initState();
|
125 argsInit<uint64_t>(PageBytes, INTREG_SP0);
126 for (int i = 0; i < contextIds.size(); i++) {
127 ThreadContext * tc = system->getThreadContext(contextIds[i]);
128 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
129 cpsr.mode = MODE_EL0T;
130 tc->setMiscReg(MISCREG_CPSR, cpsr);
131 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
132 // Enable the floating point coprocessors.
133 cpacr.cp10 = 0x3;
134 cpacr.cp11 = 0x3;
135 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
136 // Generically enable floating point support.
137 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
138 fpexc.en = 1;
139 tc->setMiscReg(MISCREG_FPEXC, fpexc);
140 }
141}
142
143template <class IntType>
144void
| 125 argsInit<uint64_t>(PageBytes, INTREG_SP0);
126 for (int i = 0; i < contextIds.size(); i++) {
127 ThreadContext * tc = system->getThreadContext(contextIds[i]);
128 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
129 cpsr.mode = MODE_EL0T;
130 tc->setMiscReg(MISCREG_CPSR, cpsr);
131 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
132 // Enable the floating point coprocessors.
133 cpacr.cp10 = 0x3;
134 cpacr.cp11 = 0x3;
135 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
136 // Generically enable floating point support.
137 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
138 fpexc.en = 1;
139 tc->setMiscReg(MISCREG_FPEXC, fpexc);
140 }
141}
142
143template <class IntType>
144void
|
145ArmLiveProcess::argsInit(int pageSize, IntRegIndex spIndex)
| 145ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
|
146{
147 int intSize = sizeof(IntType);
148
149 typedef AuxVector<IntType> auxv_t;
150 std::vector<auxv_t> auxv;
151
152 string filename;
153 if (argv.size() < 1)
154 filename = "";
155 else
156 filename = argv[0];
157
158 //We want 16 byte alignment
159 uint64_t align = 16;
160
161 // Patch the ld_bias for dynamic executables.
162 updateBias();
163
164 // load object file into target memory
165 objFile->loadSections(initVirtMem);
166
167 enum ArmCpuFeature {
168 Arm_Swp = 1 << 0,
169 Arm_Half = 1 << 1,
170 Arm_Thumb = 1 << 2,
171 Arm_26Bit = 1 << 3,
172 Arm_FastMult = 1 << 4,
173 Arm_Fpa = 1 << 5,
174 Arm_Vfp = 1 << 6,
175 Arm_Edsp = 1 << 7,
176 Arm_Java = 1 << 8,
177 Arm_Iwmmxt = 1 << 9,
178 Arm_Crunch = 1 << 10,
179 Arm_ThumbEE = 1 << 11,
180 Arm_Neon = 1 << 12,
181 Arm_Vfpv3 = 1 << 13,
182 Arm_Vfpv3d16 = 1 << 14
183 };
184
185 //Setup the auxilliary vectors. These will already have endian conversion.
186 //Auxilliary vectors are loaded only for elf formatted executables.
187 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
188 if (elfObject) {
189
190 if (objFile->getOpSys() == ObjectFile::Linux) {
191 IntType features =
192 Arm_Swp |
193 Arm_Half |
194 Arm_Thumb |
195// Arm_26Bit |
196 Arm_FastMult |
197// Arm_Fpa |
198 Arm_Vfp |
199 Arm_Edsp |
200// Arm_Java |
201// Arm_Iwmmxt |
202// Arm_Crunch |
203 Arm_ThumbEE |
204 Arm_Neon |
205 Arm_Vfpv3 |
206 Arm_Vfpv3d16 |
207 0;
208
209 //Bits which describe the system hardware capabilities
210 //XXX Figure out what these should be
211 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
212 //Frequency at which times() increments
213 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
214 //Whether to enable "secure mode" in the executable
215 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
216 // Pointer to 16 bytes of random data
217 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
218 //The filename of the program
219 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
220 //The string "v71" -- ARM v7 architecture
221 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
222 }
223
224 //The system page size
225 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes));
226 // For statically linked executables, this is the virtual address of the
227 // program header tables if they appear in the executable image
228 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
229 // This is the size of a program header entry from the elf file.
230 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
231 // This is the number of program headers from the original elf file.
232 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
233 // This is the base address of the ELF interpreter; it should be
234 // zero for static executables or contain the base address for
235 // dynamic executables.
236 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
237 //XXX Figure out what this should be.
238 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
239 //The entry point to the program
240 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
241 //Different user and group IDs
242 auxv.push_back(auxv_t(M5_AT_UID, uid()));
243 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
244 auxv.push_back(auxv_t(M5_AT_GID, gid()));
245 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
246 }
247
248 //Figure out how big the initial stack nedes to be
249
250 // A sentry NULL void pointer at the top of the stack.
251 int sentry_size = intSize;
252
253 string platform = "v71";
254 int platform_size = platform.size() + 1;
255
256 // Bytes for AT_RANDOM above, we'll just keep them 0
257 int aux_random_size = 16; // as per the specification
258
259 // The aux vectors are put on the stack in two groups. The first group are
260 // the vectors that are generated as the elf is loaded. The second group
261 // are the ones that were computed ahead of time and include the platform
262 // string.
263 int aux_data_size = filename.size() + 1;
264
265 int env_data_size = 0;
266 for (int i = 0; i < envp.size(); ++i) {
267 env_data_size += envp[i].size() + 1;
268 }
269 int arg_data_size = 0;
270 for (int i = 0; i < argv.size(); ++i) {
271 arg_data_size += argv[i].size() + 1;
272 }
273
274 int info_block_size =
275 sentry_size + env_data_size + arg_data_size +
276 aux_data_size + platform_size + aux_random_size;
277
278 //Each auxilliary vector is two 4 byte words
279 int aux_array_size = intSize * 2 * (auxv.size() + 1);
280
281 int envp_array_size = intSize * (envp.size() + 1);
282 int argv_array_size = intSize * (argv.size() + 1);
283
284 int argc_size = intSize;
285
286 //Figure out the size of the contents of the actual initial frame
287 int frame_size =
288 info_block_size +
289 aux_array_size +
290 envp_array_size +
291 argv_array_size +
292 argc_size;
293
294 //There needs to be padding after the auxiliary vector data so that the
295 //very bottom of the stack is aligned properly.
296 int partial_size = frame_size;
297 int aligned_partial_size = roundUp(partial_size, align);
298 int aux_padding = aligned_partial_size - partial_size;
299
300 int space_needed = frame_size + aux_padding;
301
302 stack_min = stack_base - space_needed;
303 stack_min = roundDown(stack_min, align);
304 stack_size = stack_base - stack_min;
305
306 // map memory
307 allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
308
309 // map out initial stack contents
310 IntType sentry_base = stack_base - sentry_size;
311 IntType aux_data_base = sentry_base - aux_data_size;
312 IntType env_data_base = aux_data_base - env_data_size;
313 IntType arg_data_base = env_data_base - arg_data_size;
314 IntType platform_base = arg_data_base - platform_size;
315 IntType aux_random_base = platform_base - aux_random_size;
316 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
317 IntType envp_array_base = auxv_array_base - envp_array_size;
318 IntType argv_array_base = envp_array_base - argv_array_size;
319 IntType argc_base = argv_array_base - argc_size;
320
321 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
322 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
323 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
324 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
325 DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
326 DPRINTF(Stack, "0x%x - platform base\n", platform_base);
327 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
328 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
329 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
330 DPRINTF(Stack, "0x%x - argc \n", argc_base);
331 DPRINTF(Stack, "0x%x - stack min\n", stack_min);
332
333 // write contents to stack
334
335 // figure out argc
336 IntType argc = argv.size();
337 IntType guestArgc = ArmISA::htog(argc);
338
339 //Write out the sentry void *
340 IntType sentry_NULL = 0;
341 initVirtMem.writeBlob(sentry_base,
342 (uint8_t*)&sentry_NULL, sentry_size);
343
344 //Fix up the aux vectors which point to other data
345 for (int i = auxv.size() - 1; i >= 0; i--) {
346 if (auxv[i].a_type == M5_AT_PLATFORM) {
347 auxv[i].a_val = platform_base;
348 initVirtMem.writeString(platform_base, platform.c_str());
349 } else if (auxv[i].a_type == M5_AT_EXECFN) {
350 auxv[i].a_val = aux_data_base;
351 initVirtMem.writeString(aux_data_base, filename.c_str());
352 } else if (auxv[i].a_type == M5_AT_RANDOM) {
353 auxv[i].a_val = aux_random_base;
354 // Just leave the value 0, we don't want randomness
355 }
356 }
357
358 //Copy the aux stuff
359 for (int x = 0; x < auxv.size(); x++) {
360 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
361 (uint8_t*)&(auxv[x].a_type), intSize);
362 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
363 (uint8_t*)&(auxv[x].a_val), intSize);
364 }
365 //Write out the terminating zeroed auxilliary vector
366 const uint64_t zero = 0;
367 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
368 (uint8_t*)&zero, 2 * intSize);
369
370 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
371 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
372
373 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
374
375 ThreadContext *tc = system->getThreadContext(contextIds[0]);
376 //Set the stack pointer register
377 tc->setIntReg(spIndex, stack_min);
378 //A pointer to a function to run when the program exits. We'll set this
379 //to zero explicitly to make sure this isn't used.
380 tc->setIntReg(ArgumentReg0, 0);
381 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
382 if (argv.size() > 0) {
383 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
384 argv[argv.size() - 1].size() - 1);
385 } else {
386 tc->setIntReg(ArgumentReg1, 0);
387 }
388 if (envp.size() > 0) {
389 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
390 envp[envp.size() - 1].size() - 1);
391 } else {
392 tc->setIntReg(ArgumentReg2, 0);
393 }
394
395 PCState pc;
396 pc.thumb(arch == ObjectFile::Thumb);
397 pc.nextThumb(pc.thumb());
398 pc.aarch64(arch == ObjectFile::Arm64);
399 pc.nextAArch64(pc.aarch64());
400 pc.set(getStartPC() & ~mask(1));
401 tc->pcState(pc);
402
403 //Align the "stack_min" to a page boundary.
404 stack_min = roundDown(stack_min, pageSize);
405}
406
407ArmISA::IntReg
| 146{
147 int intSize = sizeof(IntType);
148
149 typedef AuxVector<IntType> auxv_t;
150 std::vector<auxv_t> auxv;
151
152 string filename;
153 if (argv.size() < 1)
154 filename = "";
155 else
156 filename = argv[0];
157
158 //We want 16 byte alignment
159 uint64_t align = 16;
160
161 // Patch the ld_bias for dynamic executables.
162 updateBias();
163
164 // load object file into target memory
165 objFile->loadSections(initVirtMem);
166
167 enum ArmCpuFeature {
168 Arm_Swp = 1 << 0,
169 Arm_Half = 1 << 1,
170 Arm_Thumb = 1 << 2,
171 Arm_26Bit = 1 << 3,
172 Arm_FastMult = 1 << 4,
173 Arm_Fpa = 1 << 5,
174 Arm_Vfp = 1 << 6,
175 Arm_Edsp = 1 << 7,
176 Arm_Java = 1 << 8,
177 Arm_Iwmmxt = 1 << 9,
178 Arm_Crunch = 1 << 10,
179 Arm_ThumbEE = 1 << 11,
180 Arm_Neon = 1 << 12,
181 Arm_Vfpv3 = 1 << 13,
182 Arm_Vfpv3d16 = 1 << 14
183 };
184
185 //Setup the auxilliary vectors. These will already have endian conversion.
186 //Auxilliary vectors are loaded only for elf formatted executables.
187 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
188 if (elfObject) {
189
190 if (objFile->getOpSys() == ObjectFile::Linux) {
191 IntType features =
192 Arm_Swp |
193 Arm_Half |
194 Arm_Thumb |
195// Arm_26Bit |
196 Arm_FastMult |
197// Arm_Fpa |
198 Arm_Vfp |
199 Arm_Edsp |
200// Arm_Java |
201// Arm_Iwmmxt |
202// Arm_Crunch |
203 Arm_ThumbEE |
204 Arm_Neon |
205 Arm_Vfpv3 |
206 Arm_Vfpv3d16 |
207 0;
208
209 //Bits which describe the system hardware capabilities
210 //XXX Figure out what these should be
211 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
212 //Frequency at which times() increments
213 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
214 //Whether to enable "secure mode" in the executable
215 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
216 // Pointer to 16 bytes of random data
217 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
218 //The filename of the program
219 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
220 //The string "v71" -- ARM v7 architecture
221 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
222 }
223
224 //The system page size
225 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes));
226 // For statically linked executables, this is the virtual address of the
227 // program header tables if they appear in the executable image
228 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
229 // This is the size of a program header entry from the elf file.
230 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
231 // This is the number of program headers from the original elf file.
232 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
233 // This is the base address of the ELF interpreter; it should be
234 // zero for static executables or contain the base address for
235 // dynamic executables.
236 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
237 //XXX Figure out what this should be.
238 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
239 //The entry point to the program
240 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
241 //Different user and group IDs
242 auxv.push_back(auxv_t(M5_AT_UID, uid()));
243 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
244 auxv.push_back(auxv_t(M5_AT_GID, gid()));
245 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
246 }
247
248 //Figure out how big the initial stack nedes to be
249
250 // A sentry NULL void pointer at the top of the stack.
251 int sentry_size = intSize;
252
253 string platform = "v71";
254 int platform_size = platform.size() + 1;
255
256 // Bytes for AT_RANDOM above, we'll just keep them 0
257 int aux_random_size = 16; // as per the specification
258
259 // The aux vectors are put on the stack in two groups. The first group are
260 // the vectors that are generated as the elf is loaded. The second group
261 // are the ones that were computed ahead of time and include the platform
262 // string.
263 int aux_data_size = filename.size() + 1;
264
265 int env_data_size = 0;
266 for (int i = 0; i < envp.size(); ++i) {
267 env_data_size += envp[i].size() + 1;
268 }
269 int arg_data_size = 0;
270 for (int i = 0; i < argv.size(); ++i) {
271 arg_data_size += argv[i].size() + 1;
272 }
273
274 int info_block_size =
275 sentry_size + env_data_size + arg_data_size +
276 aux_data_size + platform_size + aux_random_size;
277
278 //Each auxilliary vector is two 4 byte words
279 int aux_array_size = intSize * 2 * (auxv.size() + 1);
280
281 int envp_array_size = intSize * (envp.size() + 1);
282 int argv_array_size = intSize * (argv.size() + 1);
283
284 int argc_size = intSize;
285
286 //Figure out the size of the contents of the actual initial frame
287 int frame_size =
288 info_block_size +
289 aux_array_size +
290 envp_array_size +
291 argv_array_size +
292 argc_size;
293
294 //There needs to be padding after the auxiliary vector data so that the
295 //very bottom of the stack is aligned properly.
296 int partial_size = frame_size;
297 int aligned_partial_size = roundUp(partial_size, align);
298 int aux_padding = aligned_partial_size - partial_size;
299
300 int space_needed = frame_size + aux_padding;
301
302 stack_min = stack_base - space_needed;
303 stack_min = roundDown(stack_min, align);
304 stack_size = stack_base - stack_min;
305
306 // map memory
307 allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
308
309 // map out initial stack contents
310 IntType sentry_base = stack_base - sentry_size;
311 IntType aux_data_base = sentry_base - aux_data_size;
312 IntType env_data_base = aux_data_base - env_data_size;
313 IntType arg_data_base = env_data_base - arg_data_size;
314 IntType platform_base = arg_data_base - platform_size;
315 IntType aux_random_base = platform_base - aux_random_size;
316 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
317 IntType envp_array_base = auxv_array_base - envp_array_size;
318 IntType argv_array_base = envp_array_base - argv_array_size;
319 IntType argc_base = argv_array_base - argc_size;
320
321 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
322 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
323 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
324 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
325 DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
326 DPRINTF(Stack, "0x%x - platform base\n", platform_base);
327 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
328 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
329 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
330 DPRINTF(Stack, "0x%x - argc \n", argc_base);
331 DPRINTF(Stack, "0x%x - stack min\n", stack_min);
332
333 // write contents to stack
334
335 // figure out argc
336 IntType argc = argv.size();
337 IntType guestArgc = ArmISA::htog(argc);
338
339 //Write out the sentry void *
340 IntType sentry_NULL = 0;
341 initVirtMem.writeBlob(sentry_base,
342 (uint8_t*)&sentry_NULL, sentry_size);
343
344 //Fix up the aux vectors which point to other data
345 for (int i = auxv.size() - 1; i >= 0; i--) {
346 if (auxv[i].a_type == M5_AT_PLATFORM) {
347 auxv[i].a_val = platform_base;
348 initVirtMem.writeString(platform_base, platform.c_str());
349 } else if (auxv[i].a_type == M5_AT_EXECFN) {
350 auxv[i].a_val = aux_data_base;
351 initVirtMem.writeString(aux_data_base, filename.c_str());
352 } else if (auxv[i].a_type == M5_AT_RANDOM) {
353 auxv[i].a_val = aux_random_base;
354 // Just leave the value 0, we don't want randomness
355 }
356 }
357
358 //Copy the aux stuff
359 for (int x = 0; x < auxv.size(); x++) {
360 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
361 (uint8_t*)&(auxv[x].a_type), intSize);
362 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
363 (uint8_t*)&(auxv[x].a_val), intSize);
364 }
365 //Write out the terminating zeroed auxilliary vector
366 const uint64_t zero = 0;
367 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
368 (uint8_t*)&zero, 2 * intSize);
369
370 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
371 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
372
373 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
374
375 ThreadContext *tc = system->getThreadContext(contextIds[0]);
376 //Set the stack pointer register
377 tc->setIntReg(spIndex, stack_min);
378 //A pointer to a function to run when the program exits. We'll set this
379 //to zero explicitly to make sure this isn't used.
380 tc->setIntReg(ArgumentReg0, 0);
381 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
382 if (argv.size() > 0) {
383 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
384 argv[argv.size() - 1].size() - 1);
385 } else {
386 tc->setIntReg(ArgumentReg1, 0);
387 }
388 if (envp.size() > 0) {
389 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
390 envp[envp.size() - 1].size() - 1);
391 } else {
392 tc->setIntReg(ArgumentReg2, 0);
393 }
394
395 PCState pc;
396 pc.thumb(arch == ObjectFile::Thumb);
397 pc.nextThumb(pc.thumb());
398 pc.aarch64(arch == ObjectFile::Arm64);
399 pc.nextAArch64(pc.aarch64());
400 pc.set(getStartPC() & ~mask(1));
401 tc->pcState(pc);
402
403 //Align the "stack_min" to a page boundary.
404 stack_min = roundDown(stack_min, pageSize);
405}
406
407ArmISA::IntReg
|
408ArmLiveProcess32::getSyscallArg(ThreadContext *tc, int &i)
| 408ArmProcess32::getSyscallArg(ThreadContext *tc, int &i)
|
409{
410 assert(i < 6);
411 return tc->readIntReg(ArgumentReg0 + i++);
412}
413
414ArmISA::IntReg
| 409{
410 assert(i < 6);
411 return tc->readIntReg(ArgumentReg0 + i++);
412}
413
414ArmISA::IntReg
|
415ArmLiveProcess64::getSyscallArg(ThreadContext *tc, int &i)
| 415ArmProcess64::getSyscallArg(ThreadContext *tc, int &i)
|
416{
417 assert(i < 8);
418 return tc->readIntReg(ArgumentReg0 + i++);
419}
420
421ArmISA::IntReg
| 416{
417 assert(i < 8);
418 return tc->readIntReg(ArgumentReg0 + i++);
419}
420
421ArmISA::IntReg
|
422ArmLiveProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
| 422ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
|
423{
424 assert(width == 32 || width == 64);
425 if (width == 32)
426 return getSyscallArg(tc, i);
427
428 // 64 bit arguments are passed starting in an even register
429 if (i % 2 != 0)
430 i++;
431
432 // Registers r0-r6 can be used
433 assert(i < 5);
434 uint64_t val;
435 val = tc->readIntReg(ArgumentReg0 + i++);
436 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
437 return val;
438}
439
440ArmISA::IntReg
| 423{
424 assert(width == 32 || width == 64);
425 if (width == 32)
426 return getSyscallArg(tc, i);
427
428 // 64 bit arguments are passed starting in an even register
429 if (i % 2 != 0)
430 i++;
431
432 // Registers r0-r6 can be used
433 assert(i < 5);
434 uint64_t val;
435 val = tc->readIntReg(ArgumentReg0 + i++);
436 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
437 return val;
438}
439
440ArmISA::IntReg
|
441ArmLiveProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
| 441ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
|
442{
443 return getSyscallArg(tc, i);
444}
445
446
447void
| 442{
443 return getSyscallArg(tc, i);
444}
445
446
447void
|
448ArmLiveProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
| 448ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
|
449{
450 assert(i < 6);
451 tc->setIntReg(ArgumentReg0 + i, val);
452}
453
454void
| 449{
450 assert(i < 6);
451 tc->setIntReg(ArgumentReg0 + i, val);
452}
453
454void
|
455ArmLiveProcess64::setSyscallArg(ThreadContext *tc,
456 int i, ArmISA::IntReg val)
| 455ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
|
457{
458 assert(i < 8);
459 tc->setIntReg(ArgumentReg0 + i, val);
460}
461
462void
| 456{
457 assert(i < 8);
458 tc->setIntReg(ArgumentReg0 + i, val);
459}
460
461void
|
463ArmLiveProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
| 462ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
|
464{
465
466 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
467 // Decode return value
468 if (sysret.encodedValue() >= 0)
469 // FreeBSD checks the carry bit to determine if syscall is succeeded
470 tc->setCCReg(CCREG_C, 0);
471 else {
472 sysret = -sysret.encodedValue();
473 }
474 }
475
476 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
477}
478
479void
| 463{
464
465 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
466 // Decode return value
467 if (sysret.encodedValue() >= 0)
468 // FreeBSD checks the carry bit to determine if syscall is succeeded
469 tc->setCCReg(CCREG_C, 0);
470 else {
471 sysret = -sysret.encodedValue();
472 }
473 }
474
475 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
476}
477
478void
|
480ArmLiveProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
| 479ArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
|
481{
482
483 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
484 // Decode return value
485 if (sysret.encodedValue() >= 0)
486 // FreeBSD checks the carry bit to determine if syscall is succeeded
487 tc->setCCReg(CCREG_C, 0);
488 else {
489 sysret = -sysret.encodedValue();
490 }
491 }
492
493 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
494}
| 480{
481
482 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
483 // Decode return value
484 if (sysret.encodedValue() >= 0)
485 // FreeBSD checks the carry bit to determine if syscall is succeeded
486 tc->setCCReg(CCREG_C, 0);
487 else {
488 sysret = -sysret.encodedValue();
489 }
490 }
491
492 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
493}
|