1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 * Ali Saidi
42 */
43
44#include "arch/arm/isa_traits.hh"
45#include "arch/arm/process.hh"
46#include "arch/arm/types.hh"
47#include "base/loader/elf_object.hh"
48#include "base/loader/object_file.hh"
49#include "base/misc.hh"
50#include "cpu/thread_context.hh"
51#include "debug/Stack.hh"
52#include "mem/page_table.hh"
53#include "sim/byteswap.hh"
54#include "sim/process_impl.hh"
55#include "sim/system.hh"
56
57using namespace std;
58using namespace ArmISA;
59
60ArmLiveProcess::ArmLiveProcess(LiveProcessParams *params, ObjectFile *objFile,
61 ObjectFile::Arch _arch)
62 : LiveProcess(params, objFile), arch(_arch)
63{
64}
65
66ArmLiveProcess32::ArmLiveProcess32(LiveProcessParams *params,
67 ObjectFile *objFile, ObjectFile::Arch _arch)
68 : ArmLiveProcess(params, objFile, _arch)
69{
70 stack_base = 0xbf000000L;
71
72 // Set pointer for next thread stack. Reserve 8M for main stack.
73 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
74
75 // Set up break point (Top of Heap)
76 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
77 brk_point = roundUp(brk_point, PageBytes);
78
79 // Set up region for mmaps. For now, start at bottom of kuseg space.
| 1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 * Ali Saidi
42 */
43
44#include "arch/arm/isa_traits.hh"
45#include "arch/arm/process.hh"
46#include "arch/arm/types.hh"
47#include "base/loader/elf_object.hh"
48#include "base/loader/object_file.hh"
49#include "base/misc.hh"
50#include "cpu/thread_context.hh"
51#include "debug/Stack.hh"
52#include "mem/page_table.hh"
53#include "sim/byteswap.hh"
54#include "sim/process_impl.hh"
55#include "sim/system.hh"
56
57using namespace std;
58using namespace ArmISA;
59
60ArmLiveProcess::ArmLiveProcess(LiveProcessParams *params, ObjectFile *objFile,
61 ObjectFile::Arch _arch)
62 : LiveProcess(params, objFile), arch(_arch)
63{
64}
65
66ArmLiveProcess32::ArmLiveProcess32(LiveProcessParams *params,
67 ObjectFile *objFile, ObjectFile::Arch _arch)
68 : ArmLiveProcess(params, objFile, _arch)
69{
70 stack_base = 0xbf000000L;
71
72 // Set pointer for next thread stack. Reserve 8M for main stack.
73 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
74
75 // Set up break point (Top of Heap)
76 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
77 brk_point = roundUp(brk_point, PageBytes);
78
79 // Set up region for mmaps. For now, start at bottom of kuseg space.
|
98}
99
100void
101ArmLiveProcess32::initState()
102{
103 LiveProcess::initState();
104 argsInit<uint32_t>(PageBytes, INTREG_SP);
105 for (int i = 0; i < contextIds.size(); i++) {
106 ThreadContext * tc = system->getThreadContext(contextIds[i]);
107 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
108 // Enable the floating point coprocessors.
109 cpacr.cp10 = 0x3;
110 cpacr.cp11 = 0x3;
111 tc->setMiscReg(MISCREG_CPACR, cpacr);
112 // Generically enable floating point support.
113 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
114 fpexc.en = 1;
115 tc->setMiscReg(MISCREG_FPEXC, fpexc);
116 }
117}
118
119void
120ArmLiveProcess64::initState()
121{
122 LiveProcess::initState();
123 argsInit<uint64_t>(PageBytes, INTREG_SP0);
124 for (int i = 0; i < contextIds.size(); i++) {
125 ThreadContext * tc = system->getThreadContext(contextIds[i]);
126 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
127 cpsr.mode = MODE_EL0T;
128 tc->setMiscReg(MISCREG_CPSR, cpsr);
129 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
130 // Enable the floating point coprocessors.
131 cpacr.cp10 = 0x3;
132 cpacr.cp11 = 0x3;
133 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
134 // Generically enable floating point support.
135 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
136 fpexc.en = 1;
137 tc->setMiscReg(MISCREG_FPEXC, fpexc);
138 }
139}
140
141template <class IntType>
142void
143ArmLiveProcess::argsInit(int pageSize, IntRegIndex spIndex)
144{
145 int intSize = sizeof(IntType);
146
147 typedef AuxVector<IntType> auxv_t;
148 std::vector<auxv_t> auxv;
149
150 string filename;
151 if (argv.size() < 1)
152 filename = "";
153 else
154 filename = argv[0];
155
156 //We want 16 byte alignment
157 uint64_t align = 16;
158
159 // load object file into target memory
160 objFile->loadSections(initVirtMem);
161
162 enum ArmCpuFeature {
163 Arm_Swp = 1 << 0,
164 Arm_Half = 1 << 1,
165 Arm_Thumb = 1 << 2,
166 Arm_26Bit = 1 << 3,
167 Arm_FastMult = 1 << 4,
168 Arm_Fpa = 1 << 5,
169 Arm_Vfp = 1 << 6,
170 Arm_Edsp = 1 << 7,
171 Arm_Java = 1 << 8,
172 Arm_Iwmmxt = 1 << 9,
173 Arm_Crunch = 1 << 10,
174 Arm_ThumbEE = 1 << 11,
175 Arm_Neon = 1 << 12,
176 Arm_Vfpv3 = 1 << 13,
177 Arm_Vfpv3d16 = 1 << 14
178 };
179
180 //Setup the auxilliary vectors. These will already have endian conversion.
181 //Auxilliary vectors are loaded only for elf formatted executables.
182 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
183 if (elfObject) {
184
185 if (objFile->getOpSys() == ObjectFile::Linux) {
186 IntType features =
187 Arm_Swp |
188 Arm_Half |
189 Arm_Thumb |
190// Arm_26Bit |
191 Arm_FastMult |
192// Arm_Fpa |
193 Arm_Vfp |
194 Arm_Edsp |
195// Arm_Java |
196// Arm_Iwmmxt |
197// Arm_Crunch |
198 Arm_ThumbEE |
199 Arm_Neon |
200 Arm_Vfpv3 |
201 Arm_Vfpv3d16 |
202 0;
203
204 //Bits which describe the system hardware capabilities
205 //XXX Figure out what these should be
206 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
207 //Frequency at which times() increments
208 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
209 //Whether to enable "secure mode" in the executable
210 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
211 // Pointer to 16 bytes of random data
212 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
213 //The filename of the program
214 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
215 //The string "v71" -- ARM v7 architecture
216 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
217 }
218
219 //The system page size
220 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes));
221 // For statically linked executables, this is the virtual address of the
222 // program header tables if they appear in the executable image
223 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
224 // This is the size of a program header entry from the elf file.
225 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
226 // This is the number of program headers from the original elf file.
227 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
228 //This is the address of the elf "interpreter", It should be set
229 //to 0 for regular executables. It should be something else
230 //(not sure what) for dynamic libraries.
231 auxv.push_back(auxv_t(M5_AT_BASE, 0));
232 //XXX Figure out what this should be.
233 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
234 //The entry point to the program
235 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
236 //Different user and group IDs
237 auxv.push_back(auxv_t(M5_AT_UID, uid()));
238 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
239 auxv.push_back(auxv_t(M5_AT_GID, gid()));
240 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
241 }
242
243 //Figure out how big the initial stack nedes to be
244
245 // A sentry NULL void pointer at the top of the stack.
246 int sentry_size = intSize;
247
248 string platform = "v71";
249 int platform_size = platform.size() + 1;
250
251 // Bytes for AT_RANDOM above, we'll just keep them 0
252 int aux_random_size = 16; // as per the specification
253
254 // The aux vectors are put on the stack in two groups. The first group are
255 // the vectors that are generated as the elf is loaded. The second group
256 // are the ones that were computed ahead of time and include the platform
257 // string.
258 int aux_data_size = filename.size() + 1;
259
260 int env_data_size = 0;
261 for (int i = 0; i < envp.size(); ++i) {
262 env_data_size += envp[i].size() + 1;
263 }
264 int arg_data_size = 0;
265 for (int i = 0; i < argv.size(); ++i) {
266 arg_data_size += argv[i].size() + 1;
267 }
268
269 int info_block_size =
270 sentry_size + env_data_size + arg_data_size +
271 aux_data_size + platform_size + aux_random_size;
272
273 //Each auxilliary vector is two 4 byte words
274 int aux_array_size = intSize * 2 * (auxv.size() + 1);
275
276 int envp_array_size = intSize * (envp.size() + 1);
277 int argv_array_size = intSize * (argv.size() + 1);
278
279 int argc_size = intSize;
280
281 //Figure out the size of the contents of the actual initial frame
282 int frame_size =
283 info_block_size +
284 aux_array_size +
285 envp_array_size +
286 argv_array_size +
287 argc_size;
288
289 //There needs to be padding after the auxiliary vector data so that the
290 //very bottom of the stack is aligned properly.
291 int partial_size = frame_size;
292 int aligned_partial_size = roundUp(partial_size, align);
293 int aux_padding = aligned_partial_size - partial_size;
294
295 int space_needed = frame_size + aux_padding;
296
297 stack_min = stack_base - space_needed;
298 stack_min = roundDown(stack_min, align);
299 stack_size = stack_base - stack_min;
300
301 // map memory
302 allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
303
304 // map out initial stack contents
305 IntType sentry_base = stack_base - sentry_size;
306 IntType aux_data_base = sentry_base - aux_data_size;
307 IntType env_data_base = aux_data_base - env_data_size;
308 IntType arg_data_base = env_data_base - arg_data_size;
309 IntType platform_base = arg_data_base - platform_size;
310 IntType aux_random_base = platform_base - aux_random_size;
311 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
312 IntType envp_array_base = auxv_array_base - envp_array_size;
313 IntType argv_array_base = envp_array_base - argv_array_size;
314 IntType argc_base = argv_array_base - argc_size;
315
316 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
317 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
318 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
319 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
320 DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
321 DPRINTF(Stack, "0x%x - platform base\n", platform_base);
322 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
323 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
324 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
325 DPRINTF(Stack, "0x%x - argc \n", argc_base);
326 DPRINTF(Stack, "0x%x - stack min\n", stack_min);
327
328 // write contents to stack
329
330 // figure out argc
331 IntType argc = argv.size();
332 IntType guestArgc = ArmISA::htog(argc);
333
334 //Write out the sentry void *
335 IntType sentry_NULL = 0;
336 initVirtMem.writeBlob(sentry_base,
337 (uint8_t*)&sentry_NULL, sentry_size);
338
339 //Fix up the aux vectors which point to other data
340 for (int i = auxv.size() - 1; i >= 0; i--) {
341 if (auxv[i].a_type == M5_AT_PLATFORM) {
342 auxv[i].a_val = platform_base;
343 initVirtMem.writeString(platform_base, platform.c_str());
344 } else if (auxv[i].a_type == M5_AT_EXECFN) {
345 auxv[i].a_val = aux_data_base;
346 initVirtMem.writeString(aux_data_base, filename.c_str());
347 } else if (auxv[i].a_type == M5_AT_RANDOM) {
348 auxv[i].a_val = aux_random_base;
349 // Just leave the value 0, we don't want randomness
350 }
351 }
352
353 //Copy the aux stuff
354 for (int x = 0; x < auxv.size(); x++) {
355 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
356 (uint8_t*)&(auxv[x].a_type), intSize);
357 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
358 (uint8_t*)&(auxv[x].a_val), intSize);
359 }
360 //Write out the terminating zeroed auxilliary vector
361 const uint64_t zero = 0;
362 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
363 (uint8_t*)&zero, 2 * intSize);
364
365 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
366 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
367
368 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
369
370 ThreadContext *tc = system->getThreadContext(contextIds[0]);
371 //Set the stack pointer register
372 tc->setIntReg(spIndex, stack_min);
373 //A pointer to a function to run when the program exits. We'll set this
374 //to zero explicitly to make sure this isn't used.
375 tc->setIntReg(ArgumentReg0, 0);
376 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
377 if (argv.size() > 0) {
378 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
379 argv[argv.size() - 1].size() - 1);
380 } else {
381 tc->setIntReg(ArgumentReg1, 0);
382 }
383 if (envp.size() > 0) {
384 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
385 envp[envp.size() - 1].size() - 1);
386 } else {
387 tc->setIntReg(ArgumentReg2, 0);
388 }
389
390 PCState pc;
391 pc.thumb(arch == ObjectFile::Thumb);
392 pc.nextThumb(pc.thumb());
393 pc.aarch64(arch == ObjectFile::Arm64);
394 pc.nextAArch64(pc.aarch64());
395 pc.set(objFile->entryPoint() & ~mask(1));
396 tc->pcState(pc);
397
398 //Align the "stack_min" to a page boundary.
399 stack_min = roundDown(stack_min, pageSize);
400}
401
402ArmISA::IntReg
403ArmLiveProcess32::getSyscallArg(ThreadContext *tc, int &i)
404{
405 assert(i < 6);
406 return tc->readIntReg(ArgumentReg0 + i++);
407}
408
409ArmISA::IntReg
410ArmLiveProcess64::getSyscallArg(ThreadContext *tc, int &i)
411{
412 assert(i < 8);
413 return tc->readIntReg(ArgumentReg0 + i++);
414}
415
416ArmISA::IntReg
417ArmLiveProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
418{
419 assert(width == 32 || width == 64);
420 if (width == 32)
421 return getSyscallArg(tc, i);
422
423 // 64 bit arguments are passed starting in an even register
424 if (i % 2 != 0)
425 i++;
426
427 // Registers r0-r6 can be used
428 assert(i < 5);
429 uint64_t val;
430 val = tc->readIntReg(ArgumentReg0 + i++);
431 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
432 return val;
433}
434
435ArmISA::IntReg
436ArmLiveProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
437{
438 return getSyscallArg(tc, i);
439}
440
441
442void
443ArmLiveProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
444{
445 assert(i < 6);
446 tc->setIntReg(ArgumentReg0 + i, val);
447}
448
449void
450ArmLiveProcess64::setSyscallArg(ThreadContext *tc,
451 int i, ArmISA::IntReg val)
452{
453 assert(i < 8);
454 tc->setIntReg(ArgumentReg0 + i, val);
455}
456
457void
458ArmLiveProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
459{
460
461 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
462 // Decode return value
463 if (sysret.encodedValue() >= 0)
464 // FreeBSD checks the carry bit to determine if syscall is succeeded
465 tc->setCCReg(CCREG_C, 0);
466 else {
467 sysret = -sysret.encodedValue();
468 }
469 }
470
471 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
472}
473
474void
475ArmLiveProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
476{
477
478 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
479 // Decode return value
480 if (sysret.encodedValue() >= 0)
481 // FreeBSD checks the carry bit to determine if syscall is succeeded
482 tc->setCCReg(CCREG_C, 0);
483 else {
484 sysret = -sysret.encodedValue();
485 }
486 }
487
488 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
489}
| 98}
99
100void
101ArmLiveProcess32::initState()
102{
103 LiveProcess::initState();
104 argsInit<uint32_t>(PageBytes, INTREG_SP);
105 for (int i = 0; i < contextIds.size(); i++) {
106 ThreadContext * tc = system->getThreadContext(contextIds[i]);
107 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
108 // Enable the floating point coprocessors.
109 cpacr.cp10 = 0x3;
110 cpacr.cp11 = 0x3;
111 tc->setMiscReg(MISCREG_CPACR, cpacr);
112 // Generically enable floating point support.
113 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
114 fpexc.en = 1;
115 tc->setMiscReg(MISCREG_FPEXC, fpexc);
116 }
117}
118
119void
120ArmLiveProcess64::initState()
121{
122 LiveProcess::initState();
123 argsInit<uint64_t>(PageBytes, INTREG_SP0);
124 for (int i = 0; i < contextIds.size(); i++) {
125 ThreadContext * tc = system->getThreadContext(contextIds[i]);
126 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
127 cpsr.mode = MODE_EL0T;
128 tc->setMiscReg(MISCREG_CPSR, cpsr);
129 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
130 // Enable the floating point coprocessors.
131 cpacr.cp10 = 0x3;
132 cpacr.cp11 = 0x3;
133 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
134 // Generically enable floating point support.
135 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
136 fpexc.en = 1;
137 tc->setMiscReg(MISCREG_FPEXC, fpexc);
138 }
139}
140
141template <class IntType>
142void
143ArmLiveProcess::argsInit(int pageSize, IntRegIndex spIndex)
144{
145 int intSize = sizeof(IntType);
146
147 typedef AuxVector<IntType> auxv_t;
148 std::vector<auxv_t> auxv;
149
150 string filename;
151 if (argv.size() < 1)
152 filename = "";
153 else
154 filename = argv[0];
155
156 //We want 16 byte alignment
157 uint64_t align = 16;
158
159 // load object file into target memory
160 objFile->loadSections(initVirtMem);
161
162 enum ArmCpuFeature {
163 Arm_Swp = 1 << 0,
164 Arm_Half = 1 << 1,
165 Arm_Thumb = 1 << 2,
166 Arm_26Bit = 1 << 3,
167 Arm_FastMult = 1 << 4,
168 Arm_Fpa = 1 << 5,
169 Arm_Vfp = 1 << 6,
170 Arm_Edsp = 1 << 7,
171 Arm_Java = 1 << 8,
172 Arm_Iwmmxt = 1 << 9,
173 Arm_Crunch = 1 << 10,
174 Arm_ThumbEE = 1 << 11,
175 Arm_Neon = 1 << 12,
176 Arm_Vfpv3 = 1 << 13,
177 Arm_Vfpv3d16 = 1 << 14
178 };
179
180 //Setup the auxilliary vectors. These will already have endian conversion.
181 //Auxilliary vectors are loaded only for elf formatted executables.
182 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
183 if (elfObject) {
184
185 if (objFile->getOpSys() == ObjectFile::Linux) {
186 IntType features =
187 Arm_Swp |
188 Arm_Half |
189 Arm_Thumb |
190// Arm_26Bit |
191 Arm_FastMult |
192// Arm_Fpa |
193 Arm_Vfp |
194 Arm_Edsp |
195// Arm_Java |
196// Arm_Iwmmxt |
197// Arm_Crunch |
198 Arm_ThumbEE |
199 Arm_Neon |
200 Arm_Vfpv3 |
201 Arm_Vfpv3d16 |
202 0;
203
204 //Bits which describe the system hardware capabilities
205 //XXX Figure out what these should be
206 auxv.push_back(auxv_t(M5_AT_HWCAP, features));
207 //Frequency at which times() increments
208 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
209 //Whether to enable "secure mode" in the executable
210 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
211 // Pointer to 16 bytes of random data
212 auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
213 //The filename of the program
214 auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
215 //The string "v71" -- ARM v7 architecture
216 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
217 }
218
219 //The system page size
220 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes));
221 // For statically linked executables, this is the virtual address of the
222 // program header tables if they appear in the executable image
223 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
224 // This is the size of a program header entry from the elf file.
225 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
226 // This is the number of program headers from the original elf file.
227 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
228 //This is the address of the elf "interpreter", It should be set
229 //to 0 for regular executables. It should be something else
230 //(not sure what) for dynamic libraries.
231 auxv.push_back(auxv_t(M5_AT_BASE, 0));
232 //XXX Figure out what this should be.
233 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
234 //The entry point to the program
235 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
236 //Different user and group IDs
237 auxv.push_back(auxv_t(M5_AT_UID, uid()));
238 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
239 auxv.push_back(auxv_t(M5_AT_GID, gid()));
240 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
241 }
242
243 //Figure out how big the initial stack nedes to be
244
245 // A sentry NULL void pointer at the top of the stack.
246 int sentry_size = intSize;
247
248 string platform = "v71";
249 int platform_size = platform.size() + 1;
250
251 // Bytes for AT_RANDOM above, we'll just keep them 0
252 int aux_random_size = 16; // as per the specification
253
254 // The aux vectors are put on the stack in two groups. The first group are
255 // the vectors that are generated as the elf is loaded. The second group
256 // are the ones that were computed ahead of time and include the platform
257 // string.
258 int aux_data_size = filename.size() + 1;
259
260 int env_data_size = 0;
261 for (int i = 0; i < envp.size(); ++i) {
262 env_data_size += envp[i].size() + 1;
263 }
264 int arg_data_size = 0;
265 for (int i = 0; i < argv.size(); ++i) {
266 arg_data_size += argv[i].size() + 1;
267 }
268
269 int info_block_size =
270 sentry_size + env_data_size + arg_data_size +
271 aux_data_size + platform_size + aux_random_size;
272
273 //Each auxilliary vector is two 4 byte words
274 int aux_array_size = intSize * 2 * (auxv.size() + 1);
275
276 int envp_array_size = intSize * (envp.size() + 1);
277 int argv_array_size = intSize * (argv.size() + 1);
278
279 int argc_size = intSize;
280
281 //Figure out the size of the contents of the actual initial frame
282 int frame_size =
283 info_block_size +
284 aux_array_size +
285 envp_array_size +
286 argv_array_size +
287 argc_size;
288
289 //There needs to be padding after the auxiliary vector data so that the
290 //very bottom of the stack is aligned properly.
291 int partial_size = frame_size;
292 int aligned_partial_size = roundUp(partial_size, align);
293 int aux_padding = aligned_partial_size - partial_size;
294
295 int space_needed = frame_size + aux_padding;
296
297 stack_min = stack_base - space_needed;
298 stack_min = roundDown(stack_min, align);
299 stack_size = stack_base - stack_min;
300
301 // map memory
302 allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
303
304 // map out initial stack contents
305 IntType sentry_base = stack_base - sentry_size;
306 IntType aux_data_base = sentry_base - aux_data_size;
307 IntType env_data_base = aux_data_base - env_data_size;
308 IntType arg_data_base = env_data_base - arg_data_size;
309 IntType platform_base = arg_data_base - platform_size;
310 IntType aux_random_base = platform_base - aux_random_size;
311 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
312 IntType envp_array_base = auxv_array_base - envp_array_size;
313 IntType argv_array_base = envp_array_base - argv_array_size;
314 IntType argc_base = argv_array_base - argc_size;
315
316 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
317 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
318 DPRINTF(Stack, "0x%x - env data\n", env_data_base);
319 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
320 DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
321 DPRINTF(Stack, "0x%x - platform base\n", platform_base);
322 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
323 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
324 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
325 DPRINTF(Stack, "0x%x - argc \n", argc_base);
326 DPRINTF(Stack, "0x%x - stack min\n", stack_min);
327
328 // write contents to stack
329
330 // figure out argc
331 IntType argc = argv.size();
332 IntType guestArgc = ArmISA::htog(argc);
333
334 //Write out the sentry void *
335 IntType sentry_NULL = 0;
336 initVirtMem.writeBlob(sentry_base,
337 (uint8_t*)&sentry_NULL, sentry_size);
338
339 //Fix up the aux vectors which point to other data
340 for (int i = auxv.size() - 1; i >= 0; i--) {
341 if (auxv[i].a_type == M5_AT_PLATFORM) {
342 auxv[i].a_val = platform_base;
343 initVirtMem.writeString(platform_base, platform.c_str());
344 } else if (auxv[i].a_type == M5_AT_EXECFN) {
345 auxv[i].a_val = aux_data_base;
346 initVirtMem.writeString(aux_data_base, filename.c_str());
347 } else if (auxv[i].a_type == M5_AT_RANDOM) {
348 auxv[i].a_val = aux_random_base;
349 // Just leave the value 0, we don't want randomness
350 }
351 }
352
353 //Copy the aux stuff
354 for (int x = 0; x < auxv.size(); x++) {
355 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
356 (uint8_t*)&(auxv[x].a_type), intSize);
357 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
358 (uint8_t*)&(auxv[x].a_val), intSize);
359 }
360 //Write out the terminating zeroed auxilliary vector
361 const uint64_t zero = 0;
362 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
363 (uint8_t*)&zero, 2 * intSize);
364
365 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
366 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
367
368 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
369
370 ThreadContext *tc = system->getThreadContext(contextIds[0]);
371 //Set the stack pointer register
372 tc->setIntReg(spIndex, stack_min);
373 //A pointer to a function to run when the program exits. We'll set this
374 //to zero explicitly to make sure this isn't used.
375 tc->setIntReg(ArgumentReg0, 0);
376 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
377 if (argv.size() > 0) {
378 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
379 argv[argv.size() - 1].size() - 1);
380 } else {
381 tc->setIntReg(ArgumentReg1, 0);
382 }
383 if (envp.size() > 0) {
384 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
385 envp[envp.size() - 1].size() - 1);
386 } else {
387 tc->setIntReg(ArgumentReg2, 0);
388 }
389
390 PCState pc;
391 pc.thumb(arch == ObjectFile::Thumb);
392 pc.nextThumb(pc.thumb());
393 pc.aarch64(arch == ObjectFile::Arm64);
394 pc.nextAArch64(pc.aarch64());
395 pc.set(objFile->entryPoint() & ~mask(1));
396 tc->pcState(pc);
397
398 //Align the "stack_min" to a page boundary.
399 stack_min = roundDown(stack_min, pageSize);
400}
401
402ArmISA::IntReg
403ArmLiveProcess32::getSyscallArg(ThreadContext *tc, int &i)
404{
405 assert(i < 6);
406 return tc->readIntReg(ArgumentReg0 + i++);
407}
408
409ArmISA::IntReg
410ArmLiveProcess64::getSyscallArg(ThreadContext *tc, int &i)
411{
412 assert(i < 8);
413 return tc->readIntReg(ArgumentReg0 + i++);
414}
415
416ArmISA::IntReg
417ArmLiveProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
418{
419 assert(width == 32 || width == 64);
420 if (width == 32)
421 return getSyscallArg(tc, i);
422
423 // 64 bit arguments are passed starting in an even register
424 if (i % 2 != 0)
425 i++;
426
427 // Registers r0-r6 can be used
428 assert(i < 5);
429 uint64_t val;
430 val = tc->readIntReg(ArgumentReg0 + i++);
431 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
432 return val;
433}
434
435ArmISA::IntReg
436ArmLiveProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
437{
438 return getSyscallArg(tc, i);
439}
440
441
442void
443ArmLiveProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
444{
445 assert(i < 6);
446 tc->setIntReg(ArgumentReg0 + i, val);
447}
448
449void
450ArmLiveProcess64::setSyscallArg(ThreadContext *tc,
451 int i, ArmISA::IntReg val)
452{
453 assert(i < 8);
454 tc->setIntReg(ArgumentReg0 + i, val);
455}
456
457void
458ArmLiveProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
459{
460
461 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
462 // Decode return value
463 if (sysret.encodedValue() >= 0)
464 // FreeBSD checks the carry bit to determine if syscall is succeeded
465 tc->setCCReg(CCREG_C, 0);
466 else {
467 sysret = -sysret.encodedValue();
468 }
469 }
470
471 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
472}
473
474void
475ArmLiveProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
476{
477
478 if (objFile->getOpSys() == ObjectFile::FreeBSD) {
479 // Decode return value
480 if (sysret.encodedValue() >= 0)
481 // FreeBSD checks the carry bit to determine if syscall is succeeded
482 tc->setCCReg(CCREG_C, 0);
483 else {
484 sysret = -sysret.encodedValue();
485 }
486 }
487
488 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
489}
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