pmu.hh (13104:4a0713e11ef7) | pmu.hh (13581:b6dcd0183747) |
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1/* 2 * Copyright (c) 2011-2014, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 107 unchanged lines hidden (view full) --- 116 void setThreadContext(ThreadContext *tc) override; 117 118 /** 119 * Set a register within the PMU. 120 * 121 * @param misc_reg Register number (see miscregs.hh) 122 * @param val Value to store 123 */ | 1/* 2 * Copyright (c) 2011-2014, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 107 unchanged lines hidden (view full) --- 116 void setThreadContext(ThreadContext *tc) override; 117 118 /** 119 * Set a register within the PMU. 120 * 121 * @param misc_reg Register number (see miscregs.hh) 122 * @param val Value to store 123 */ |
124 void setMiscReg(int misc_reg, MiscReg val) override; | 124 void setMiscReg(int misc_reg, RegVal val) override; |
125 /** 126 * Read a register within the PMU. 127 * 128 * @param misc_reg Register number (see miscregs.hh) 129 * @return Register value. 130 */ | 125 /** 126 * Read a register within the PMU. 127 * 128 * @param misc_reg Register number (see miscregs.hh) 129 * @return Register value. 130 */ |
131 MiscReg readMiscReg(int misc_reg) override; | 131 RegVal readMiscReg(int misc_reg) override; |
132 133 protected: // PMU register types and constants 134 BitUnion32(PMCR_t) 135 // PMU Enable 136 Bitfield<0> e; 137 // Event counter reset 138 Bitfield<1> p; 139 // Cycle counter reset --- 51 unchanged lines hidden (view full) --- 191 /** 192 * Event type ID. 193 * 194 * See the PMU documentation for a list of architected IDs. 195 */ 196 typedef unsigned int EventTypeId; 197 198 protected: /* High-level register and interrupt handling */ | 132 133 protected: // PMU register types and constants 134 BitUnion32(PMCR_t) 135 // PMU Enable 136 Bitfield<0> e; 137 // Event counter reset 138 Bitfield<1> p; 139 // Cycle counter reset --- 51 unchanged lines hidden (view full) --- 191 /** 192 * Event type ID. 193 * 194 * See the PMU documentation for a list of architected IDs. 195 */ 196 typedef unsigned int EventTypeId; 197 198 protected: /* High-level register and interrupt handling */ |
199 MiscReg readMiscRegInt(int misc_reg); | 199 RegVal readMiscRegInt(int misc_reg); |
200 201 /** 202 * PMCR write handling 203 * 204 * The PMCR register needs special handling since writing to it 205 * changes PMU-global state (e.g., resets all counters). 206 * 207 * @param val New PMCR value --- 71 unchanged lines hidden (view full) --- 279 * 280 * This method implements a write to the PMOVSSET/PMOVSCLR registers. 281 * It is capturing change of state in the register bits so that 282 * the overflow interrupt can be raised/cleared as a side effect 283 * of the write. 284 * 285 * @param new_val New value of the Overflow Status Register 286 */ | 200 201 /** 202 * PMCR write handling 203 * 204 * The PMCR register needs special handling since writing to it 205 * changes PMU-global state (e.g., resets all counters). 206 * 207 * @param val New PMCR value --- 71 unchanged lines hidden (view full) --- 279 * 280 * This method implements a write to the PMOVSSET/PMOVSCLR registers. 281 * It is capturing change of state in the register bits so that 282 * the overflow interrupt can be raised/cleared as a side effect 283 * of the write. 284 * 285 * @param new_val New value of the Overflow Status Register 286 */ |
287 void setOverflowStatus(MiscReg new_val); | 287 void setOverflowStatus(RegVal new_val); |
288 289 protected: /* Probe handling and counter state */ 290 struct CounterState; 291 292 /** 293 * Event definition base class 294 */ 295 struct PMUEvent { --- 269 unchanged lines hidden (view full) --- 565 * counter's state has changed.. 566 * 567 * @see updateCounter() 568 */ 569 void updateAllCounters(); 570 571 protected: /* State that needs to be serialized */ 572 /** Performance Monitor Count Enable Register */ | 288 289 protected: /* Probe handling and counter state */ 290 struct CounterState; 291 292 /** 293 * Event definition base class 294 */ 295 struct PMUEvent { --- 269 unchanged lines hidden (view full) --- 565 * counter's state has changed.. 566 * 567 * @see updateCounter() 568 */ 569 void updateAllCounters(); 570 571 protected: /* State that needs to be serialized */ 572 /** Performance Monitor Count Enable Register */ |
573 MiscReg reg_pmcnten; | 573 RegVal reg_pmcnten; |
574 575 /** Performance Monitor Control Register */ 576 PMCR_t reg_pmcr; 577 578 /** Performance Monitor Selection Register */ 579 PMSELR_t reg_pmselr; 580 581 /** Performance Monitor Interrupt Enable Register */ | 574 575 /** Performance Monitor Control Register */ 576 PMCR_t reg_pmcr; 577 578 /** Performance Monitor Selection Register */ 579 PMSELR_t reg_pmselr; 580 581 /** Performance Monitor Interrupt Enable Register */ |
582 MiscReg reg_pminten; | 582 RegVal reg_pminten; |
583 584 /** Performance Monitor Overflow Status Register */ | 583 584 /** Performance Monitor Overflow Status Register */ |
585 MiscReg reg_pmovsr; | 585 RegVal reg_pmovsr; |
586 587 /** 588 * Performance counter ID register 589 * 590 * These registers contain a bitmask of available architected 591 * counters. 592 */ 593 uint64_t reg_pmceid0; --- 17 unchanged lines hidden (view full) --- 611 /** The event that implements the software increment **/ 612 SWIncrementEvent *swIncrementEvent; 613 614 protected: /* Configuration and constants */ 615 /** Constant (configuration-dependent) part of the PMCR */ 616 PMCR_t reg_pmcr_conf; 617 618 /** PMCR write mask when accessed from the guest */ | 586 587 /** 588 * Performance counter ID register 589 * 590 * These registers contain a bitmask of available architected 591 * counters. 592 */ 593 uint64_t reg_pmceid0; --- 17 unchanged lines hidden (view full) --- 611 /** The event that implements the software increment **/ 612 SWIncrementEvent *swIncrementEvent; 613 614 protected: /* Configuration and constants */ 615 /** Constant (configuration-dependent) part of the PMCR */ 616 PMCR_t reg_pmcr_conf; 617 618 /** PMCR write mask when accessed from the guest */ |
619 static const MiscReg reg_pmcr_wr_mask; | 619 static const RegVal reg_pmcr_wr_mask; |
620 621 /** Performance monitor interrupt number */ 622 ArmInterruptPin *const interrupt; 623 624 /** 625 * List of event types supported by this PMU. 626 */ 627 std::map<EventTypeId, PMUEvent*> eventMap; 628}; 629 630} // namespace ArmISA 631#endif | 620 621 /** Performance monitor interrupt number */ 622 ArmInterruptPin *const interrupt; 623 624 /** 625 * List of event types supported by this PMU. 626 */ 627 std::map<EventTypeId, PMUEvent*> eventMap; 628}; 629 630} // namespace ArmISA 631#endif |