pmu.hh (11168:f98eb2da15a4) pmu.hh (12117:f50d7e4998e9)
1/*
1/*
2 * Copyright (c) 2011-2014 ARM Limited
2 * Copyright (c) 2011-2014, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 132 unchanged lines hidden (view full) ---

143 EndBitUnion(PMCR_t)
144
145 BitUnion32(PMSELR_t)
146 // Performance counter selector
147 Bitfield<4, 0> sel;
148 EndBitUnion(PMSELR_t)
149
150 BitUnion32(PMEVTYPER_t)
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 132 unchanged lines hidden (view full) ---

143 EndBitUnion(PMCR_t)
144
145 BitUnion32(PMSELR_t)
146 // Performance counter selector
147 Bitfield<4, 0> sel;
148 EndBitUnion(PMSELR_t)
149
150 BitUnion32(PMEVTYPER_t)
151 Bitfield<9, 0> evtCount;
151 Bitfield<15, 0> evtCount;
152
153 // Secure EL3 filtering
154 Bitfield<26> m;
155 // Non-secure EL2 mode filtering
156 Bitfield<27> nsh;
157 // Non-secure EL0 mode filtering
158 Bitfield<28> nsu;
159 // Non-secure EL1 mode filtering

--- 294 unchanged lines hidden (view full) ---

454 MiscReg reg_pminten;
455
456 /** Performance Monitor Overflow Status Register */
457 MiscReg reg_pmovsr;
458
459 /**
460 * Performance counter ID register
461 *
152
153 // Secure EL3 filtering
154 Bitfield<26> m;
155 // Non-secure EL2 mode filtering
156 Bitfield<27> nsh;
157 // Non-secure EL0 mode filtering
158 Bitfield<28> nsu;
159 // Non-secure EL1 mode filtering

--- 294 unchanged lines hidden (view full) ---

454 MiscReg reg_pminten;
455
456 /** Performance Monitor Overflow Status Register */
457 MiscReg reg_pmovsr;
458
459 /**
460 * Performance counter ID register
461 *
462 * This register contains a bitmask of available architected
462 * These registers contain a bitmask of available architected
463 * counters.
464 */
463 * counters.
464 */
465 uint64_t reg_pmceid;
465 uint64_t reg_pmceid0;
466 uint64_t reg_pmceid1;
466
467 /** Remainder part when the clock counter is divided by 64 */
468 unsigned clock_remainder;
469
470 /** State of all general-purpose counters supported by PMU */
471 std::vector<CounterState> counters;
472 /** State of the cycle counter */
473 CounterState cycleCounter;

--- 33 unchanged lines hidden --- 		467
468 /** Remainder part when the clock counter is divided by 64 */
469 unsigned clock_remainder;
470
471 /** State of all general-purpose counters supported by PMU */
472 std::vector<CounterState> counters;
473 /** State of the cycle counter */
474 CounterState cycleCounter;

--- 33 unchanged lines hidden ---