pmu.cc (13637:503ee472c371) pmu.cc (13638:76cb1cecc057)
1/*
2 * Copyright (c) 2011-2014, 2017-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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62 reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
63 reg_pmceid0(0),reg_pmceid1(0),
64 clock_remainder(0),
65 maximumCounterCount(p->eventCounters),
66 cycleCounter(*this, maximumCounterCount),
67 cycleCounterEventId(p->cycleEventId),
68 swIncrementEvent(nullptr),
69 reg_pmcr_conf(0),
1/*
2 * Copyright (c) 2011-2014, 2017-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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62 reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
63 reg_pmceid0(0),reg_pmceid1(0),
64 clock_remainder(0),
65 maximumCounterCount(p->eventCounters),
66 cycleCounter(*this, maximumCounterCount),
67 cycleCounterEventId(p->cycleEventId),
68 swIncrementEvent(nullptr),
69 reg_pmcr_conf(0),
70 interrupt(p->interrupt->get())
70 interrupt(nullptr),
71{
72 DPRINTF(PMUVerbose, "Initializing the PMU.\n");
73
74 if (maximumCounterCount > 31) {
75 fatal("The PMU can only accept 31 counters, %d counters requested.\n",
76 maximumCounterCount);
77 }
78
71{
72 DPRINTF(PMUVerbose, "Initializing the PMU.\n");
73
74 if (maximumCounterCount > 31) {
75 fatal("The PMU can only accept 31 counters, %d counters requested.\n",
76 maximumCounterCount);
77 }
78
79 warn_if(!interrupt, "ARM PMU: No interrupt specified, interrupt " \
79 warn_if(!p->interrupt, "ARM PMU: No interrupt specified, interrupt " \
80 "delivery disabled.\n");
81
82 /* Setup the performance counter ID registers */
83 reg_pmcr_conf.imp = 0x41; // ARM Ltd.
84 reg_pmcr_conf.idcode = 0x00;
85 reg_pmcr_conf.n = p->eventCounters;
86
87 // Setup the hard-coded cycle counter, which is equivalent to

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92PMU::~PMU()
93{
94}
95
96void
97PMU::setThreadContext(ThreadContext *tc)
98{
99 DPRINTF(PMUVerbose, "Assigning PMU to ContextID %i.\n", tc->contextId());
80 "delivery disabled.\n");
81
82 /* Setup the performance counter ID registers */
83 reg_pmcr_conf.imp = 0x41; // ARM Ltd.
84 reg_pmcr_conf.idcode = 0x00;
85 reg_pmcr_conf.n = p->eventCounters;
86
87 // Setup the hard-coded cycle counter, which is equivalent to

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92PMU::~PMU()
93{
94}
95
96void
97PMU::setThreadContext(ThreadContext *tc)
98{
99 DPRINTF(PMUVerbose, "Assigning PMU to ContextID %i.\n", tc->contextId());
100 if (interrupt)
101 interrupt->setThreadContext(tc);
100 auto pmu_params = static_cast<const ArmPMUParams *>(params());
101
102 if (pmu_params->interrupt)
103 interrupt = pmu_params->interrupt->get(tc);
102}
103
104void
105PMU::addSoftwareIncrementEvent(unsigned int id)
106{
107 auto old_event = eventMap.find(id);
108 DPRINTF(PMUVerbose, "PMU: Adding SW increment event with id '0x%x'\n", id);
109

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105
106void
107PMU::addSoftwareIncrementEvent(unsigned int id)
108{
109 auto old_event = eventMap.find(id);
110 DPRINTF(PMUVerbose, "PMU: Adding SW increment event with id '0x%x'\n", id);
111

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