pmu.cc (12974:b840a646cfbd) pmu.cc (13104:4a0713e11ef7)
1/*
2 * Copyright (c) 2011-2014, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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209 case MISCREG_PMCNTENCLR_EL0:
210 case MISCREG_PMCNTENCLR:
211 reg_pmcnten &= ~val;
212 updateAllCounters();
213 return;
214
215 case MISCREG_PMOVSCLR_EL0:
216 case MISCREG_PMOVSR:
1/*
2 * Copyright (c) 2011-2014, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 200 unchanged lines hidden (view full) ---

209 case MISCREG_PMCNTENCLR_EL0:
210 case MISCREG_PMCNTENCLR:
211 reg_pmcnten &= ~val;
212 updateAllCounters();
213 return;
214
215 case MISCREG_PMOVSCLR_EL0:
216 case MISCREG_PMOVSR:
217 reg_pmovsr &= ~val;
217 setOverflowStatus(reg_pmovsr & ~val);
218 return;
219
220 case MISCREG_PMSWINC_EL0:
221 case MISCREG_PMSWINC:
222 if (swIncrementEvent) {
223 swIncrementEvent->write(val);
224 }
225 return;

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281
282 case MISCREG_PMINTENCLR_EL1:
283 case MISCREG_PMINTENCLR:
284 reg_pminten &= ~val;
285 return;
286
287 case MISCREG_PMOVSSET_EL0:
288 case MISCREG_PMOVSSET:
218 return;
219
220 case MISCREG_PMSWINC_EL0:
221 case MISCREG_PMSWINC:
222 if (swIncrementEvent) {
223 swIncrementEvent->write(val);
224 }
225 return;

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281
282 case MISCREG_PMINTENCLR_EL1:
283 case MISCREG_PMINTENCLR:
284 reg_pminten &= ~val;
285 return;
286
287 case MISCREG_PMOVSSET_EL0:
288 case MISCREG_PMOVSSET:
289 reg_pmovsr |= val;
289 setOverflowStatus(reg_pmovsr | val);
290 return;
291
292 default:
293 panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]);
294 }
295
296 warn("Not doing anything for write to miscreg %s\n",
297 miscRegName[misc_reg]);

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640 // need to update the probes the counter is using.
641 if (id != PMCCNTR && old_event_id != val.evtCount) {
642 ctr.eventId = val.evtCount;
643 updateCounter(ctr);
644 }
645}
646
647void
290 return;
291
292 default:
293 panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]);
294 }
295
296 warn("Not doing anything for write to miscreg %s\n",
297 miscRegName[misc_reg]);

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640 // need to update the probes the counter is using.
641 if (id != PMCCNTR && old_event_id != val.evtCount) {
642 ctr.eventId = val.evtCount;
643 updateCounter(ctr);
644 }
645}
646
647void
648PMU::setOverflowStatus(MiscReg new_val)
649{
650 const bool int_old = reg_pmovsr != 0;
651 const bool int_new = new_val != 0;
652
653 reg_pmovsr = new_val;
654 if (int_old && !int_new) {
655 clearInterrupt();
656 } else if (!int_old && int_new && (reg_pminten & reg_pmovsr)) {
657 raiseInterrupt();
658 }
659}
660
661void
648PMU::raiseInterrupt()
649{
650 if (interrupt) {
651 DPRINTF(PMUVerbose, "Delivering PMU interrupt.\n");
652 interrupt->raise();
653 } else {
654 warn_once("Dropping PMU interrupt as no interrupt has "
655 "been specified\n");
656 }
657}
658
659void
662PMU::raiseInterrupt()
663{
664 if (interrupt) {
665 DPRINTF(PMUVerbose, "Delivering PMU interrupt.\n");
666 interrupt->raise();
667 } else {
668 warn_once("Dropping PMU interrupt as no interrupt has "
669 "been specified\n");
670 }
671}
672
673void
674PMU::clearInterrupt()
675{
676 if (interrupt) {
677 DPRINTF(PMUVerbose, "Clearing PMU interrupt.\n");
678 interrupt->clear();
679 } else {
680 warn_once("Dropping PMU interrupt as no interrupt has "
681 "been specified\n");
682 }
683}
684
685void
660PMU::serialize(CheckpointOut &cp) const
661{
662 DPRINTF(Checkpoint, "Serializing Arm PMU\n");
663
664 SERIALIZE_SCALAR(reg_pmcr);
665 SERIALIZE_SCALAR(reg_pmcnten);
666 SERIALIZE_SCALAR(reg_pmselr);
667 SERIALIZE_SCALAR(reg_pminten);

--- 121 unchanged lines hidden --- 		686PMU::serialize(CheckpointOut &cp) const
687{
688 DPRINTF(Checkpoint, "Serializing Arm PMU\n");
689
690 SERIALIZE_SCALAR(reg_pmcr);
691 SERIALIZE_SCALAR(reg_pmcnten);
692 SERIALIZE_SCALAR(reg_pmselr);
693 SERIALIZE_SCALAR(reg_pminten);

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