pmu.cc (12286:fb69c03c88e1) pmu.cc (12973:78a7bbc23c29)
1/*
1/*
2 * Copyright (c) 2011-2014, 2017 ARM Limited
2 * Copyright (c) 2011-2014, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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45#include "arch/arm/isa.hh"
46#include "arch/arm/utility.hh"
47#include "base/trace.hh"
48#include "cpu/base.hh"
49#include "debug/Checkpoint.hh"
50#include "debug/PMUVerbose.hh"
51#include "dev/arm/base_gic.hh"
52#include "dev/arm/generic_timer.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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45#include "arch/arm/isa.hh"
46#include "arch/arm/utility.hh"
47#include "base/trace.hh"
48#include "cpu/base.hh"
49#include "debug/Checkpoint.hh"
50#include "debug/PMUVerbose.hh"
51#include "dev/arm/base_gic.hh"
52#include "dev/arm/generic_timer.hh"
53#include "dev/arm/realview.hh"
54#include "params/ArmPMU.hh"
55
56namespace ArmISA {
57
58const MiscReg PMU::reg_pmcr_wr_mask = 0x39;
59
60PMU::PMU(const ArmPMUParams *p)
61 : SimObject(p), BaseISADevice(),
62 reg_pmcnten(0), reg_pmcr(0),
63 reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
64 reg_pmceid0(0),reg_pmceid1(0),
65 clock_remainder(0),
66 maximumCounterCount(p->eventCounters),
67 cycleCounter(*this, maximumCounterCount),
68 cycleCounterEventId(p->cycleEventId),
69 swIncrementEvent(nullptr),
70 reg_pmcr_conf(0),
53#include "params/ArmPMU.hh"
54
55namespace ArmISA {
56
57const MiscReg PMU::reg_pmcr_wr_mask = 0x39;
58
59PMU::PMU(const ArmPMUParams *p)
60 : SimObject(p), BaseISADevice(),
61 reg_pmcnten(0), reg_pmcr(0),
62 reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
63 reg_pmceid0(0),reg_pmceid1(0),
64 clock_remainder(0),
65 maximumCounterCount(p->eventCounters),
66 cycleCounter(*this, maximumCounterCount),
67 cycleCounterEventId(p->cycleEventId),
68 swIncrementEvent(nullptr),
69 reg_pmcr_conf(0),
71 pmuInterrupt(p->pmuInterrupt),
72 platform(p->platform)
70 interrupt(p->interrupt)
73{
74 DPRINTF(PMUVerbose, "Initializing the PMU.\n");
75
76 if (maximumCounterCount > 31) {
77 fatal("The PMU can only accept 31 counters, %d counters requested.\n",
78 maximumCounterCount);
79 }
80
71{
72 DPRINTF(PMUVerbose, "Initializing the PMU.\n");
73
74 if (maximumCounterCount > 31) {
75 fatal("The PMU can only accept 31 counters, %d counters requested.\n",
76 maximumCounterCount);
77 }
78
79 warn_if(!interrupt, "ARM PMU: No interrupt specified, interrupt " \
80 "delivery disabled.\n");
81
81 /* Setup the performance counter ID registers */
82 reg_pmcr_conf.imp = 0x41; // ARM Ltd.
83 reg_pmcr_conf.idcode = 0x00;
84 reg_pmcr_conf.n = p->eventCounters;
85
86 // Setup the hard-coded cycle counter, which is equivalent to
87 // architected counter event type 0x11.
88 cycleCounter.eventId = 0x11;
89}
90
91PMU::~PMU()
92{
93}
94
95void
82 /* Setup the performance counter ID registers */
83 reg_pmcr_conf.imp = 0x41; // ARM Ltd.
84 reg_pmcr_conf.idcode = 0x00;
85 reg_pmcr_conf.n = p->eventCounters;
86
87 // Setup the hard-coded cycle counter, which is equivalent to
88 // architected counter event type 0x11.
89 cycleCounter.eventId = 0x11;
90}
91
92PMU::~PMU()
93{
94}
95
96void
97PMU::setThreadContext(ThreadContext *tc)
98{
99 DPRINTF(PMUVerbose, "Assigning PMU to ContextID %i.\n", tc->contextId());
100 if (interrupt)
101 interrupt->setThreadContext(tc);
102}
103
104void
96PMU::addSoftwareIncrementEvent(unsigned int id)
97{
98 auto old_event = eventMap.find(id);
99 DPRINTF(PMUVerbose, "PMU: Adding SW increment event with id '0x%x'\n", id);
100
101 if (swIncrementEvent) {
102 fatal_if(old_event == eventMap.end() ||
103 old_event->second != swIncrementEvent,

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633 ctr.eventId = val.evtCount;
634 updateCounter(ctr);
635 }
636}
637
638void
639PMU::raiseInterrupt()
640{
105PMU::addSoftwareIncrementEvent(unsigned int id)
106{
107 auto old_event = eventMap.find(id);
108 DPRINTF(PMUVerbose, "PMU: Adding SW increment event with id '0x%x'\n", id);
109
110 if (swIncrementEvent) {
111 fatal_if(old_event == eventMap.end() ||
112 old_event->second != swIncrementEvent,

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642 ctr.eventId = val.evtCount;
643 updateCounter(ctr);
644 }
645}
646
647void
648PMU::raiseInterrupt()
649{
641 RealView *rv(dynamic_cast<RealView *>(platform));
642 if (!rv || !rv->gic) {
643 warn_once("ARM PMU: GIC missing, can't raise interrupt.\n");
644 return;
650 if (interrupt) {
651 DPRINTF(PMUVerbose, "Delivering PMU interrupt.\n");
652 interrupt->raise();
653 } else {
654 warn_once("Dropping PMU interrupt as no interrupt has "
655 "been specified\n");
645 }
656 }
646
647 DPRINTF(PMUVerbose, "Delivering PMU interrupt.\n");
648 rv->gic->sendInt(pmuInterrupt);
649}
650
651void
652PMU::serialize(CheckpointOut &cp) const
653{
654 DPRINTF(Checkpoint, "Serializing Arm PMU\n");
655
656 SERIALIZE_SCALAR(reg_pmcr);

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658
659void
660PMU::serialize(CheckpointOut &cp) const
661{
662 DPRINTF(Checkpoint, "Serializing Arm PMU\n");
663
664 SERIALIZE_SCALAR(reg_pmcr);

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