pmu.cc (12042:870f0d5c0ced) pmu.cc (12117:f50d7e4998e9)
1/*
1/*
2 * Copyright (c) 2011-2014 ARM Limited
2 * Copyright (c) 2011-2014, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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54namespace ArmISA {
55
56const MiscReg PMU::reg_pmcr_wr_mask = 0x39;
57
58PMU::PMU(const ArmPMUParams *p)
59 : SimObject(p), BaseISADevice(),
60 reg_pmcnten(0), reg_pmcr(0),
61 reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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54namespace ArmISA {
55
56const MiscReg PMU::reg_pmcr_wr_mask = 0x39;
57
58PMU::PMU(const ArmPMUParams *p)
59 : SimObject(p), BaseISADevice(),
60 reg_pmcnten(0), reg_pmcr(0),
61 reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
62 reg_pmceid(0),
62 reg_pmceid0(0),reg_pmceid1(0),
63 clock_remainder(0),
64 counters(p->eventCounters),
65 reg_pmcr_conf(0),
66 pmuInterrupt(p->pmuInterrupt),
67 platform(p->platform)
68{
69 DPRINTF(PMUVerbose, "Initializing the PMU.\n");
70

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89
90void
91PMU::addEventProbe(unsigned int id, SimObject *obj, const char *probe_name)
92{
93 DPRINTF(PMUVerbose, "PMU: Adding event type '0x%x' as probe %s:%s\n",
94 id, obj->name(), probe_name);
95 pmuEventTypes.insert(std::make_pair(id, EventType(obj, probe_name)));
96
63 clock_remainder(0),
64 counters(p->eventCounters),
65 reg_pmcr_conf(0),
66 pmuInterrupt(p->pmuInterrupt),
67 platform(p->platform)
68{
69 DPRINTF(PMUVerbose, "Initializing the PMU.\n");
70

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89
90void
91PMU::addEventProbe(unsigned int id, SimObject *obj, const char *probe_name)
92{
93 DPRINTF(PMUVerbose, "PMU: Adding event type '0x%x' as probe %s:%s\n",
94 id, obj->name(), probe_name);
95 pmuEventTypes.insert(std::make_pair(id, EventType(obj, probe_name)));
96
97 // Flag the event as available in the PMCEID register if it is an
98 // architected event.
99 if (id < 0x40)
100 reg_pmceid |= (ULL(1) << id);
97 // Flag the event as available in the corresponding PMCEID register if it
98 // is an architected event.
99 if (id < 0x20) {
100 reg_pmceid0 |= ((uint64_t)1) << id;
101 } else if (id > 0x20 && id < 0x40) {
102 reg_pmceid1 |= ((uint64_t)1) << (id - 0x20);
103 } else if (id >= 0x4000 && id < 0x4020) {
104 reg_pmceid0 |= ((uint64_t)1) << (id - 0x4000 + 32);
105 } else if (id >= 0x4020 && id < 0x4040) {
106 reg_pmceid1 |= ((uint64_t)1) << (id - 0x4020 + 32);
107 }
101}
102
103void
104PMU::drainResume()
105{
106 // Re-attach enabled counters after a resume in case they changed.
107 updateAllCounters();
108}

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149 case MISCREG_PMCCNTR:
150 cycleCounter.value = val;
151 return;
152
153 case MISCREG_PMSELR_EL0:
154 case MISCREG_PMSELR:
155 reg_pmselr = val;
156 return;
108}
109
110void
111PMU::drainResume()
112{
113 // Re-attach enabled counters after a resume in case they changed.
114 updateAllCounters();
115}

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156 case MISCREG_PMCCNTR:
157 cycleCounter.value = val;
158 return;
159
160 case MISCREG_PMSELR_EL0:
161 case MISCREG_PMSELR:
162 reg_pmselr = val;
163 return;
157
164 //TODO: implement MISCREF_PMCEID{2,3}
158 case MISCREG_PMCEID0_EL0:
159 case MISCREG_PMCEID0:
160 case MISCREG_PMCEID1_EL0:
161 case MISCREG_PMCEID1:
162 // Ignore writes
163 return;
164
165 case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:

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251 case MISCREG_PMSWINC_EL0:
252 case MISCREG_PMSWINC: // Software Increment Register (RAZ)
253 return 0;
254
255 case MISCREG_PMSELR:
256 return reg_pmselr;
257
258 case MISCREG_PMCEID0_EL0:
165 case MISCREG_PMCEID0_EL0:
166 case MISCREG_PMCEID0:
167 case MISCREG_PMCEID1_EL0:
168 case MISCREG_PMCEID1:
169 // Ignore writes
170 return;
171
172 case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:

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258 case MISCREG_PMSWINC_EL0:
259 case MISCREG_PMSWINC: // Software Increment Register (RAZ)
260 return 0;
261
262 case MISCREG_PMSELR:
263 return reg_pmselr;
264
265 case MISCREG_PMCEID0_EL0:
259 case MISCREG_PMCEID0: // Common Event ID register
260 return reg_pmceid & 0xFFFFFFFF;
266 return reg_pmceid0;
261
262 case MISCREG_PMCEID1_EL0:
267
268 case MISCREG_PMCEID1_EL0:
269 return reg_pmceid1;
270
271 //TODO: implement MISCREF_PMCEID{2,3}
272 case MISCREG_PMCEID0: // Common Event ID register
273 return reg_pmceid0 & 0xFFFFFFFF;
274
263 case MISCREG_PMCEID1: // Common Event ID register
275 case MISCREG_PMCEID1: // Common Event ID register
264 return (reg_pmceid >> 32) & 0xFFFFFFFF;
276 return reg_pmceid1 & 0xFFFFFFFF;
265
266 case MISCREG_PMCCNTR_EL0:
267 return cycleCounter.value;
268
269 case MISCREG_PMCCNTR:
270 return cycleCounter.value & 0xFFFFFFFF;
271
272 case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:

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517{
518 DPRINTF(Checkpoint, "Serializing Arm PMU\n");
519
520 SERIALIZE_SCALAR(reg_pmcr);
521 SERIALIZE_SCALAR(reg_pmcnten);
522 SERIALIZE_SCALAR(reg_pmselr);
523 SERIALIZE_SCALAR(reg_pminten);
524 SERIALIZE_SCALAR(reg_pmovsr);
277
278 case MISCREG_PMCCNTR_EL0:
279 return cycleCounter.value;
280
281 case MISCREG_PMCCNTR:
282 return cycleCounter.value & 0xFFFFFFFF;
283
284 case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:

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529{
530 DPRINTF(Checkpoint, "Serializing Arm PMU\n");
531
532 SERIALIZE_SCALAR(reg_pmcr);
533 SERIALIZE_SCALAR(reg_pmcnten);
534 SERIALIZE_SCALAR(reg_pmselr);
535 SERIALIZE_SCALAR(reg_pminten);
536 SERIALIZE_SCALAR(reg_pmovsr);
525 SERIALIZE_SCALAR(reg_pmceid);
537 SERIALIZE_SCALAR(reg_pmceid0);
538 SERIALIZE_SCALAR(reg_pmceid1);
526 SERIALIZE_SCALAR(clock_remainder);
527
528 for (size_t i = 0; i < counters.size(); ++i)
529 counters[i].serializeSection(cp, csprintf("counters.%i", i));
530
531 cycleCounter.serializeSection(cp, "cycleCounter");
532}
533
534void
535PMU::unserialize(CheckpointIn &cp)
536{
537 DPRINTF(Checkpoint, "Unserializing Arm PMU\n");
538
539 UNSERIALIZE_SCALAR(reg_pmcr);
540 UNSERIALIZE_SCALAR(reg_pmcnten);
541 UNSERIALIZE_SCALAR(reg_pmselr);
542 UNSERIALIZE_SCALAR(reg_pminten);
543 UNSERIALIZE_SCALAR(reg_pmovsr);
539 SERIALIZE_SCALAR(clock_remainder);
540
541 for (size_t i = 0; i < counters.size(); ++i)
542 counters[i].serializeSection(cp, csprintf("counters.%i", i));
543
544 cycleCounter.serializeSection(cp, "cycleCounter");
545}
546
547void
548PMU::unserialize(CheckpointIn &cp)
549{
550 DPRINTF(Checkpoint, "Unserializing Arm PMU\n");
551
552 UNSERIALIZE_SCALAR(reg_pmcr);
553 UNSERIALIZE_SCALAR(reg_pmcnten);
554 UNSERIALIZE_SCALAR(reg_pmselr);
555 UNSERIALIZE_SCALAR(reg_pminten);
556 UNSERIALIZE_SCALAR(reg_pmovsr);
544 UNSERIALIZE_SCALAR(reg_pmceid);
557
558 // Old checkpoints used to store the entire PMCEID value in a
559 // single 64-bit entry (reg_pmceid). The register was extended in
560 // ARMv8.1, so we now need to store it as two 64-bit registers.
561 if (!UNSERIALIZE_OPT_SCALAR(reg_pmceid0))
562 paramIn(cp, "reg_pmceid", reg_pmceid0);
563
564 if (!UNSERIALIZE_OPT_SCALAR(reg_pmceid1))
565 reg_pmceid1 = 0;
566
545 UNSERIALIZE_SCALAR(clock_remainder);
546
547 for (size_t i = 0; i < counters.size(); ++i)
548 counters[i].unserializeSection(cp, csprintf("counters.%i", i));
549
550 cycleCounter.unserializeSection(cp, "cycleCounter");
551}
552

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568
569 for (size_t i = 0; i < counters.size(); ++i)
570 counters[i].unserializeSection(cp, csprintf("counters.%i", i));
571
572 cycleCounter.unserializeSection(cp, "cycleCounter");
573}
574

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