1/* 2 * Copyright (c) 2011-2014, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 40 unchanged lines hidden (view full) --- 49#include "debug/Checkpoint.hh" 50#include "debug/PMUVerbose.hh" 51#include "dev/arm/base_gic.hh" 52#include "dev/arm/generic_timer.hh" 53#include "params/ArmPMU.hh" 54 55namespace ArmISA { 56 |
57const RegVal PMU::reg_pmcr_wr_mask = 0x39; |
58 59PMU::PMU(const ArmPMUParams *p) 60 : SimObject(p), BaseISADevice(), 61 reg_pmcnten(0), reg_pmcr(0), 62 reg_pmselr(0), reg_pminten(0), reg_pmovsr(0), 63 reg_pmceid0(0),reg_pmceid1(0), 64 clock_remainder(0), 65 maximumCounterCount(p->eventCounters), --- 118 unchanged lines hidden (view full) --- 184 185 PMUEvent *event = getEvent(cycleCounterEventId); 186 panic_if(!event, "core cycle event is not present\n"); 187 cycleCounter.enabled = true; 188 cycleCounter.attach(event); 189} 190 191void |
192PMU::setMiscReg(int misc_reg, RegVal val) |
193{ 194 DPRINTF(PMUVerbose, "setMiscReg(%s, 0x%x)\n", 195 miscRegName[unflattenMiscReg(misc_reg)], val); 196 197 switch (unflattenMiscReg(misc_reg)) { 198 case MISCREG_PMCR_EL0: 199 case MISCREG_PMCR: 200 setControlReg(val); --- 91 unchanged lines hidden (view full) --- 292 default: 293 panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]); 294 } 295 296 warn("Not doing anything for write to miscreg %s\n", 297 miscRegName[misc_reg]); 298} 299 |
300RegVal |
301PMU::readMiscReg(int misc_reg) 302{ |
303 RegVal val(readMiscRegInt(misc_reg)); |
304 DPRINTF(PMUVerbose, "readMiscReg(%s): 0x%x\n", 305 miscRegName[unflattenMiscReg(misc_reg)], val); 306 return val; 307} 308 |
309RegVal |
310PMU::readMiscRegInt(int misc_reg) 311{ 312 misc_reg = unflattenMiscReg(misc_reg); 313 switch (misc_reg) { 314 case MISCREG_PMCR_EL0: 315 case MISCREG_PMCR: 316 return reg_pmcr_conf | (reg_pmcr & reg_pmcr_wr_mask); 317 --- 322 unchanged lines hidden (view full) --- 640 // need to update the probes the counter is using. 641 if (id != PMCCNTR && old_event_id != val.evtCount) { 642 ctr.eventId = val.evtCount; 643 updateCounter(ctr); 644 } 645} 646 647void |
648PMU::setOverflowStatus(RegVal new_val) |
649{ 650 const bool int_old = reg_pmovsr != 0; 651 const bool int_new = new_val != 0; 652 653 reg_pmovsr = new_val; 654 if (int_old && !int_new) { 655 clearInterrupt(); 656 } else if (!int_old && int_new && (reg_pminten & reg_pmovsr)) { --- 158 unchanged lines hidden --- |