2c2
< * Copyright (c) 2011-2014 ARM Limited
---
> * Copyright (c) 2011-2014, 2017 ARM Limited
62c62
< reg_pmceid(0),
---
> reg_pmceid0(0),reg_pmceid1(0),
97,100c97,107
< // Flag the event as available in the PMCEID register if it is an
< // architected event.
< if (id < 0x40)
< reg_pmceid |= (ULL(1) << id);
---
> // Flag the event as available in the corresponding PMCEID register if it
> // is an architected event.
> if (id < 0x20) {
> reg_pmceid0 |= ((uint64_t)1) << id;
> } else if (id > 0x20 && id < 0x40) {
> reg_pmceid1 |= ((uint64_t)1) << (id - 0x20);
> } else if (id >= 0x4000 && id < 0x4020) {
> reg_pmceid0 |= ((uint64_t)1) << (id - 0x4000 + 32);
> } else if (id >= 0x4020 && id < 0x4040) {
> reg_pmceid1 |= ((uint64_t)1) << (id - 0x4020 + 32);
> }
157c164
<
---
> //TODO: implement MISCREF_PMCEID{2,3}
259,260c266
< case MISCREG_PMCEID0: // Common Event ID register
< return reg_pmceid & 0xFFFFFFFF;
---
> return reg_pmceid0;
262a269,274
> return reg_pmceid1;
>
> //TODO: implement MISCREF_PMCEID{2,3}
> case MISCREG_PMCEID0: // Common Event ID register
> return reg_pmceid0 & 0xFFFFFFFF;
>
264c276
< return (reg_pmceid >> 32) & 0xFFFFFFFF;
---
> return reg_pmceid1 & 0xFFFFFFFF;
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< SERIALIZE_SCALAR(reg_pmceid);
---
> SERIALIZE_SCALAR(reg_pmceid0);
> SERIALIZE_SCALAR(reg_pmceid1);
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< UNSERIALIZE_SCALAR(reg_pmceid);
---
>
> // Old checkpoints used to store the entire PMCEID value in a
> // single 64-bit entry (reg_pmceid). The register was extended in
> // ARMv8.1, so we now need to store it as two 64-bit registers.
> if (!UNSERIALIZE_OPT_SCALAR(reg_pmceid0))
> paramIn(cp, "reg_pmceid", reg_pmceid0);
>
> if (!UNSERIALIZE_OPT_SCALAR(reg_pmceid1))
> reg_pmceid1 = 0;
>