43a44,45
> #include "arch/arm/isa.hh"
> #include "arch/arm/utility.hh"
352a355,383
> bool
> PMU::isFiltered(const CounterState &ctr) const
> {
> assert(isa);
>
> const PMEVTYPER_t filter(ctr.filter);
> const SCR scr(isa->readMiscRegNoEffect(MISCREG_SCR));
> const CPSR cpsr(isa->readMiscRegNoEffect(MISCREG_CPSR));
> const ExceptionLevel el(opModeToEL((OperatingMode)(uint8_t)cpsr.mode));
> const bool secure(inSecureState(scr, cpsr));
>
> switch (el) {
> case EL0:
> return secure ? filter.u : (filter.u != filter.nsu);
>
> case EL1:
> return secure ? filter.p : (filter.p != filter.nsk);
>
> case EL2:
> return !filter.nsh;
>
> case EL3:
> return filter.p != filter.m;
>
> default:
> panic("Unexpected execution level in PMU::isFiltered.\n");
> }
> }
>
358a390,392
> if (isFiltered(ctr))
> return;
>
437c471
< PMEVTYPER_t type(0);
---
> PMEVTYPER_t type(cs.filter);
439d472
< // TODO: Re-create filtering settings from counter state
456,457c489
< // TODO: Handle filtering (both for general purpose counters and
< // the cycle counter)
---
> const EventTypeId old_event_id(ctr.eventId);
459,461c491,496
< // If PMCCNTR Register, do not change event type. PMCCNTR can count
< // processor cycles only.
< if (id != PMCCNTR) {
---
> ctr.filter = val;
>
> // If PMCCNTR Register, do not change event type. PMCCNTR can
> // count processor cycles only. If we change the event type, we
> // need to update the probes the counter is using.
> if (id != PMCCNTR && old_event_id != val.evtCount) {