1/*
2 * Copyright (c) 2011-2014, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Dam Sunwoo
38 * Matt Horsnell
39 * Andreas Sandberg
40 */
41
42#include "arch/arm/pmu.hh"
43
44#include "arch/arm/isa.hh"
45#include "arch/arm/utility.hh"
46#include "base/trace.hh"
47#include "cpu/base.hh"
48#include "debug/Checkpoint.hh"
49#include "debug/PMUVerbose.hh"
50#include "dev/arm/base_gic.hh"
51#include "dev/arm/realview.hh"
52#include "params/ArmPMU.hh"
53
54namespace ArmISA {
55
56const MiscReg PMU::reg_pmcr_wr_mask = 0x39;
57
58PMU::PMU(const ArmPMUParams *p)
59 : SimObject(p), BaseISADevice(),
60 reg_pmcnten(0), reg_pmcr(0),
61 reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
62 reg_pmceid0(0),reg_pmceid1(0),
63 clock_remainder(0),
64 counters(p->eventCounters),
65 reg_pmcr_conf(0),
66 pmuInterrupt(p->pmuInterrupt),
67 platform(p->platform)
68{
69 DPRINTF(PMUVerbose, "Initializing the PMU.\n");
70
71 if (p->eventCounters > 31) {
72 fatal("The PMU can only accept 31 counters, %d counters requested.\n",
73 p->eventCounters);
74 }
75
76 /* Setup the performance counter ID registers */
77 reg_pmcr_conf.imp = 0x41; // ARM Ltd.
78 reg_pmcr_conf.idcode = 0x00;
79 reg_pmcr_conf.n = p->eventCounters;
80
81 // Setup the hard-coded cycle counter, which is equivalent to
82 // architected counter event type 0x11.
83 cycleCounter.eventId = 0x11;
84}
85
86PMU::~PMU()
87{
88}
89
90void
91PMU::addEventProbe(unsigned int id, SimObject *obj, const char *probe_name)
92{
93 DPRINTF(PMUVerbose, "PMU: Adding event type '0x%x' as probe %s:%s\n",
94 id, obj->name(), probe_name);
95 pmuEventTypes.insert(std::make_pair(id, EventType(obj, probe_name)));
96
97 // Flag the event as available in the corresponding PMCEID register if it
98 // is an architected event.
99 if (id < 0x20) {
100 reg_pmceid0 |= ((uint64_t)1) << id;
101 } else if (id > 0x20 && id < 0x40) {
102 reg_pmceid1 |= ((uint64_t)1) << (id - 0x20);
103 } else if (id >= 0x4000 && id < 0x4020) {
104 reg_pmceid0 |= ((uint64_t)1) << (id - 0x4000 + 32);

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110void
111PMU::drainResume()
112{
113 // Re-attach enabled counters after a resume in case they changed.
114 updateAllCounters();
115}
116
117void
118PMU::setMiscReg(int misc_reg, MiscReg val)
119{
120 DPRINTF(PMUVerbose, "setMiscReg(%s, 0x%x)\n",
121 miscRegName[unflattenMiscReg(misc_reg)], val);
122
123 switch (unflattenMiscReg(misc_reg)) {
124 case MISCREG_PMCR_EL0:
125 case MISCREG_PMCR:

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140
141 case MISCREG_PMOVSCLR_EL0:
142 case MISCREG_PMOVSR:
143 reg_pmovsr &= ~val;
144 return;
145
146 case MISCREG_PMSWINC_EL0:
147 case MISCREG_PMSWINC:
148 for (int i = 0; i < counters.size(); ++i) {
149 CounterState &ctr(getCounter(i));
150 if (ctr.enabled && (val & (1 << i))
151 && ctr.eventId == ARCH_EVENT_SW_INCR ) {
152 ++ctr.value;
153 }
154 }
155 break;
156
157 case MISCREG_PMCCNTR_EL0:
158 case MISCREG_PMCCNTR:
159 cycleCounter.value = val;
160 return;
161
162 case MISCREG_PMSELR_EL0:
163 case MISCREG_PMSELR:
164 reg_pmselr = val;
165 return;
166 //TODO: implement MISCREF_PMCEID{2,3}
167 case MISCREG_PMCEID0_EL0:

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273 //TODO: implement MISCREF_PMCEID{2,3}
274 case MISCREG_PMCEID0: // Common Event ID register
275 return reg_pmceid0 & 0xFFFFFFFF;
276
277 case MISCREG_PMCEID1: // Common Event ID register
278 return reg_pmceid1 & 0xFFFFFFFF;
279
280 case MISCREG_PMCCNTR_EL0:
281 return cycleCounter.value;
282
283 case MISCREG_PMCCNTR:
284 return cycleCounter.value & 0xFFFFFFFF;
285
286 case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
287 return getCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0);
288
289 case MISCREG_PMCCFILTR:
290 case MISCREG_PMCCFILTR_EL0:
291 return getCounterTypeRegister(PMCCNTR);
292
293 case MISCREG_PMXEVTYPER_PMCCFILTR:
294 case MISCREG_PMXEVTYPER_EL0:
295 case MISCREG_PMXEVTYPER:
296 return getCounterTypeRegister(reg_pmselr.sel);
297
298 case MISCREG_PMEVCNTR0_EL0...MISCREG_PMEVCNTR5_EL0:
299 return getCounterValue(misc_reg - MISCREG_PMEVCNTR0_EL0) & 0xFFFFFFFF;
300
301 case MISCREG_PMXEVCNTR_EL0:
302 case MISCREG_PMXEVCNTR:
303 return getCounterValue(reg_pmselr.sel) & 0xFFFFFFFF;
304
305 case MISCREG_PMUSERENR_EL0:
306 case MISCREG_PMUSERENR:
307 // TODO
308 return 0;

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329
330 if (val.p) {
331 DPRINTF(PMUVerbose, "PMU reset all events to zero.\n");
332 resetEventCounts();
333 }
334
335 if (val.c) {
336 DPRINTF(PMUVerbose, "PMU reset cycle counter to zero.\n");
337 cycleCounter.value = 0;
338 }
339
340 // Reset the clock remainder if divide by 64-mode is toggled.
341 if (reg_pmcr.d != val.d)
342 clock_remainder = 0;
343
344 reg_pmcr = val & reg_pmcr_wr_mask;
345 updateAllCounters();

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350{
351 const bool global_enable(reg_pmcr.e);
352
353 for (int i = 0; i < counters.size(); ++i) {
354 CounterState &ctr(counters[i]);
355 const bool enable(global_enable && (reg_pmcnten & (1 << i)));
356 if (ctr.enabled != enable) {
357 ctr.enabled = enable;
358 updateCounter(i, ctr);
359 }
360 }
361
362 const bool ccntr_enable(global_enable && (reg_pmcnten & (1 << PMCCNTR)));
363 if (cycleCounter.enabled != ccntr_enable) {
364 cycleCounter.enabled = ccntr_enable;
365 updateCounter(PMCCNTR, cycleCounter);
366 }
367}
368
369bool
370PMU::isFiltered(const CounterState &ctr) const
371{
372 assert(isa);
373
374 const PMEVTYPER_t filter(ctr.filter);
375 const SCR scr(isa->readMiscRegNoEffect(MISCREG_SCR));
376 const CPSR cpsr(isa->readMiscRegNoEffect(MISCREG_CPSR));
377 const ExceptionLevel el(opModeToEL((OperatingMode)(uint8_t)cpsr.mode));
378 const bool secure(inSecureState(scr, cpsr));
379
380 switch (el) {
381 case EL0:
382 return secure ? filter.u : (filter.u != filter.nsu);
383
384 case EL1:

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391 return filter.p != filter.m;
392
393 default:
394 panic("Unexpected execution level in PMU::isFiltered.\n");
395 }
396}
397
398void
399PMU::handleEvent(CounterId id, uint64_t delta)
400{
401 CounterState &ctr(getCounter(id));
402 const bool overflowed(reg_pmovsr & (1 << id));
403
404 if (isFiltered(ctr))
405 return;
406
407 // Handle the "count every 64 cycles" mode
408 if (id == PMCCNTR && reg_pmcr.d) {
409 clock_remainder += delta;
410 delta = (clock_remainder >> 6);
411 clock_remainder &= 63;
412 }
413
414 // Add delta and handle (new) overflows
415 if (ctr.add(delta) && !overflowed) {
416 DPRINTF(PMUVerbose, "PMU counter '%i' overflowed.\n", id);
417 reg_pmovsr |= (1 << id);
418 // Deliver a PMU interrupt if interrupt delivery is enabled
419 // for this counter.
420 if (reg_pminten & (1 << id))
421 raiseInterrupt();
422 }
423}
424
425void
426PMU::updateCounter(CounterId id, CounterState &ctr)
427{
428 if (!ctr.enabled) {
429 if (!ctr.listeners.empty()) {
430 DPRINTF(PMUVerbose, "updateCounter(%i): Disabling counter\n", id);
431 ctr.listeners.clear();
432 }
433 } else {
434 DPRINTF(PMUVerbose, "updateCounter(%i): Enable event id 0x%x\n",
435 id, ctr.eventId);
436
437 // Attach all probes belonging to this event
438 auto range(pmuEventTypes.equal_range(ctr.eventId));
439 for (auto it = range.first; it != range.second; ++it) {
440 const EventType &et(it->second);
441
442 DPRINTF(PMUVerbose, "\tProbe: %s:%s\n", et.obj->name(), et.name);
443 ctr.listeners.emplace_back(et.create(*this, id));
444 }
445
446 /* The SW_INCR event type is a special case which doesn't need
447 * any probes since it is controlled by software and the PMU
448 * itself.
449 */
450 if (ctr.listeners.empty() && ctr.eventId != ARCH_EVENT_SW_INCR) {
451 warn("Can't enable PMU counter of type '0x%x': "
452 "No such event type.\n", ctr.eventId);
453 }
454 }
455}
456
457
458void
459PMU::resetEventCounts()
460{
461 for (CounterState &ctr : counters)
462 ctr.value = 0;
463}
464
465void
466PMU::setCounterValue(CounterId id, uint64_t val)
467{
468 if (!isValidCounter(id)) {
469 warn_once("Can't change counter value: Counter %i does not exist.\n",
470 id);
471 return;
472 }
473
474 CounterState &ctr(getCounter(id));
475 ctr.value = val;
476}
477
478PMU::PMEVTYPER_t
479PMU::getCounterTypeRegister(CounterId id) const
480{
481 if (!isValidCounter(id))
482 return 0;
483

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504
505 ctr.filter = val;
506
507 // If PMCCNTR Register, do not change event type. PMCCNTR can
508 // count processor cycles only. If we change the event type, we
509 // need to update the probes the counter is using.
510 if (id != PMCCNTR && old_event_id != val.evtCount) {
511 ctr.eventId = val.evtCount;
512 updateCounter(reg_pmselr.sel, ctr);
513 }
514}
515
516void
517PMU::raiseInterrupt()
518{
519 RealView *rv(dynamic_cast<RealView *>(platform));
520 if (!rv || !rv->gic) {

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569 UNSERIALIZE_SCALAR(clock_remainder);
570
571 for (size_t i = 0; i < counters.size(); ++i)
572 counters[i].unserializeSection(cp, csprintf("counters.%i", i));
573
574 cycleCounter.unserializeSection(cp, "cycleCounter");
575}
576
577void
578PMU::CounterState::serialize(CheckpointOut &cp) const
579{
580 SERIALIZE_SCALAR(eventId);
581 SERIALIZE_SCALAR(value);
582 SERIALIZE_SCALAR(overflow64);
583}
584
585void
586PMU::CounterState::unserialize(CheckpointIn &cp)
587{
588 UNSERIALIZE_SCALAR(eventId);
589 UNSERIALIZE_SCALAR(value);
590 UNSERIALIZE_SCALAR(overflow64);
591}
592
593bool
594PMU::CounterState::add(uint64_t delta)
595{
596 const uint64_t msb(1ULL << (overflow64 ? 63 : 31));
597 const uint64_t old_value(value);
598
599 value += delta;
600
601 // Overflow if the msb goes from 1 to 0
602 return (old_value & msb) && !(value & msb);
603}
604
605} // namespace ArmISA
606
607ArmISA::PMU *
608ArmPMUParams::create()
609{
610 return new ArmISA::PMU(this);
611}