1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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54namespace ArmISA {
55
56const MiscReg PMU::reg_pmcr_wr_mask = 0x39;
57
58PMU::PMU(const ArmPMUParams *p)
59 : SimObject(p), BaseISADevice(),
60 reg_pmcnten(0), reg_pmcr(0),
61 reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
62 reg_pmceid(0),
63 clock_remainder(0),
64 counters(p->eventCounters),
65 reg_pmcr_conf(0),
66 pmuInterrupt(p->pmuInterrupt),
67 platform(p->platform)
68{
69 DPRINTF(PMUVerbose, "Initializing the PMU.\n");
70

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89
90void
91PMU::addEventProbe(unsigned int id, SimObject *obj, const char *probe_name)
92{
93 DPRINTF(PMUVerbose, "PMU: Adding event type '0x%x' as probe %s:%s\n",
94 id, obj->name(), probe_name);
95 pmuEventTypes.insert(std::make_pair(id, EventType(obj, probe_name)));
96
97 // Flag the event as available in the PMCEID register if it is an
98 // architected event.
99 if (id < 0x40)
100 reg_pmceid |= (ULL(1) << id);
101}
102
103void
104PMU::drainResume()
105{
106 // Re-attach enabled counters after a resume in case they changed.
107 updateAllCounters();
108}

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149 case MISCREG_PMCCNTR:
150 cycleCounter.value = val;
151 return;
152
153 case MISCREG_PMSELR_EL0:
154 case MISCREG_PMSELR:
155 reg_pmselr = val;
156 return;
157
158 case MISCREG_PMCEID0_EL0:
159 case MISCREG_PMCEID0:
160 case MISCREG_PMCEID1_EL0:
161 case MISCREG_PMCEID1:
162 // Ignore writes
163 return;
164
165 case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:

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251 case MISCREG_PMSWINC_EL0:
252 case MISCREG_PMSWINC: // Software Increment Register (RAZ)
253 return 0;
254
255 case MISCREG_PMSELR:
256 return reg_pmselr;
257
258 case MISCREG_PMCEID0_EL0:
259 case MISCREG_PMCEID0: // Common Event ID register
260 return reg_pmceid & 0xFFFFFFFF;
261
262 case MISCREG_PMCEID1_EL0:
263 case MISCREG_PMCEID1: // Common Event ID register
264 return (reg_pmceid >> 32) & 0xFFFFFFFF;
265
266 case MISCREG_PMCCNTR_EL0:
267 return cycleCounter.value;
268
269 case MISCREG_PMCCNTR:
270 return cycleCounter.value & 0xFFFFFFFF;
271
272 case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:

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517{
518 DPRINTF(Checkpoint, "Serializing Arm PMU\n");
519
520 SERIALIZE_SCALAR(reg_pmcr);
521 SERIALIZE_SCALAR(reg_pmcnten);
522 SERIALIZE_SCALAR(reg_pmselr);
523 SERIALIZE_SCALAR(reg_pminten);
524 SERIALIZE_SCALAR(reg_pmovsr);
525 SERIALIZE_SCALAR(reg_pmceid);
526 SERIALIZE_SCALAR(clock_remainder);
527
528 for (size_t i = 0; i < counters.size(); ++i)
529 counters[i].serializeSection(cp, csprintf("counters.%i", i));
530
531 cycleCounter.serializeSection(cp, "cycleCounter");
532}
533
534void
535PMU::unserialize(CheckpointIn &cp)
536{
537 DPRINTF(Checkpoint, "Unserializing Arm PMU\n");
538
539 UNSERIALIZE_SCALAR(reg_pmcr);
540 UNSERIALIZE_SCALAR(reg_pmcnten);
541 UNSERIALIZE_SCALAR(reg_pmselr);
542 UNSERIALIZE_SCALAR(reg_pminten);
543 UNSERIALIZE_SCALAR(reg_pmovsr);
544 UNSERIALIZE_SCALAR(reg_pmceid);
545 UNSERIALIZE_SCALAR(clock_remainder);
546
547 for (size_t i = 0; i < counters.size(); ++i)
548 counters[i].unserializeSection(cp, csprintf("counters.%i", i));
549
550 cycleCounter.unserializeSection(cp, "cycleCounter");
551}
552

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