pagetable.hh (7402:84a13fca7205) pagetable.hh (7404:bfc74724914e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 23 unchanged lines hidden (view full) ---

32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 * Steve Reinhardt
42 * Ali Saidi
40 * Authors: Ali Saidi
43 */
44
45#ifndef __ARCH_ARM_PAGETABLE_H__
46#define __ARCH_ARM_PAGETABLE_H__
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"

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68
69 void unserialize(Checkpoint *cp, const std::string &section)
70 {
71 panic("Need to implement PTE serialization\n");
72 }
73
74};
75
41 */
42
43#ifndef __ARCH_ARM_PAGETABLE_H__
44#define __ARCH_ARM_PAGETABLE_H__
45
46#include "arch/arm/isa_traits.hh"
47#include "arch/arm/utility.hh"
48#include "arch/arm/vtophys.hh"

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66
67 void unserialize(Checkpoint *cp, const std::string &section)
68 {
69 panic("Need to implement PTE serialization\n");
70 }
71
72};
73
74struct TlbRange
75{
76 Addr va;
77 Addr size;
78 int contextId;
79 bool global;
80
81 inline bool
82 operator<(const TlbRange &r2) const
83 {
84 if (!(global || r2.global)) {
85 if (contextId < r2.contextId)
86 return true;
87 else if (contextId > r2.contextId)
88 return false;
89 }
90
91 if (va < r2.va)
92 return true;
93 return false;
94 }
95
96 inline bool
97 operator==(const TlbRange &r2) const
98 {
99 return va == r2.va &&
100 size == r2.size &&
101 contextId == r2.contextId &&
102 global == r2.global;
103 }
104};
105
106
76// ITB/DTB table entry
77struct TlbEntry
78{
107// ITB/DTB table entry
108struct TlbEntry
109{
79 Addr tag; // virtual page number tag
80 Addr ppn; // physical page number
81 uint8_t asn; // address space number
82 bool valid; // valid page table entry
110 public:
111 enum MemoryType {
112 StronglyOrdered,
113 Device,
114 Normal
115 };
116 enum DomainType {
117 DomainNoAccess = 0,
118 DomainClient,
119 DomainReserved,
120 DomainManager
121 };
83
122
123 // Matching variables
124 Addr pfn;
125 Addr size; // Size of this entry, == Type of TLB Rec
126 Addr vpn; // Virtual Page Number
127 uint32_t asid; // Address Space Identifier
128 uint8_t N; // Number of bits in pagesize
129 bool global;
130 bool valid;
84
131
85 //Construct an entry that maps to physical address addr.
132 // Type of memory
133 bool nonCacheable; // Can we wrap this in mtype?
134 bool sNp; // Section descriptor
135
136 // Access permissions
137 bool xn; // Execute Never
138 uint8_t ap:3; // Access permissions bits
139 uint8_t domain:4; // Access Domain
140
141 TlbRange range; // For fast TLB searching
142
143 //Construct an entry that maps to physical address addr for SE mode
86 TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
87 {
144 TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
145 {
88 tag = _vaddr >> PageShift;
89 ppn = _paddr >> PageShift;
90 asn = _asn;
146 pfn = _paddr >> PageShift;
147 size = PageBytes - 1;
148 asid = _asn;
149 global = false;
91 valid = true;
150 valid = true;
151
152 vpn = _vaddr >> PageShift;
153
154 nonCacheable = sNp = false;
155
156 xn = 0;
157 ap = 0; // ???
158 domain = DomainClient; //???
92 }
93
94 TlbEntry()
95 {}
96
97 void
98 updateVaddr(Addr new_vaddr)
99 {
159 }
160
161 TlbEntry()
162 {}
163
164 void
165 updateVaddr(Addr new_vaddr)
166 {
100 tag = new_vaddr >> PageShift;
167 vpn = new_vaddr >> PageShift;
101 }
102
103 Addr
104 pageStart()
105 {
168 }
169
170 Addr
171 pageStart()
172 {
106 return ppn << PageShift;
173 return pfn << PageShift;
107 }
108
174 }
175
176 bool
177 match(Addr va, uint8_t cid)
178 {
179 Addr v = vpn << N;
180 if (valid && va >= v && va <= v + size && (global || cid == asid))
181 return true;
182 return false;
183 }
184
185 Addr
186 pAddr(Addr va)
187 {
188 return (pfn << N) | (va & size);
189 }
190
109 void serialize(std::ostream &os) { panic("Need to Implement\n"); }
110 void unserialize(Checkpoint *cp, const std::string &section)
111 { panic("Need to Implement\n");}
112};
113
114
115
116};
117#endif // __ARCH_ARM_PAGETABLE_H__
118
191 void serialize(std::ostream &os) { panic("Need to Implement\n"); }
192 void unserialize(Checkpoint *cp, const std::string &section)
193 { panic("Need to Implement\n");}
194};
195
196
197
198};
199#endif // __ARCH_ARM_PAGETABLE_H__
200