1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 34 unchanged lines hidden (view full) ---

43#ifndef __ARCH_ARM_PAGETABLE_H__
44#define __ARCH_ARM_PAGETABLE_H__
45
46#include "arch/arm/isa_traits.hh"
47#include "arch/arm/utility.hh"
48#include "arch/arm/vtophys.hh"
49#include "config/full_system.hh"
50
51namespace ArmISA {
52
53struct VAddr
54{
55 VAddr(Addr a) { panic("not implemented yet."); }
56};
57
58

--- 7 unchanged lines hidden (view full) ---

66
67 void unserialize(Checkpoint *cp, const std::string &section)
68 {
69 panic("Need to implement PTE serialization\n");
70 }
71
72};
73
74struct TlbRange
75{
76 Addr va;
77 Addr size;
78 int contextId;
79 bool global;
80
81 inline bool
82 operator<(const TlbRange &r2) const
83 {
84 if (!(global || r2.global)) {
85 if (contextId < r2.contextId)
86 return true;
87 else if (contextId > r2.contextId)
88 return false;
89 }
90
91 if (va < r2.va)
92 return true;
93 return false;
94 }
95
96 inline bool
97 operator==(const TlbRange &r2) const
98 {
99 return va == r2.va &&
100 size == r2.size &&
101 contextId == r2.contextId &&
102 global == r2.global;
103 }
104};
105
106
107// ITB/DTB table entry
108struct TlbEntry
109{
110 public:
111 enum MemoryType {
112 StronglyOrdered,
113 Device,
114 Normal

--- 23 unchanged lines hidden (view full) ---

138 uint8_t innerAttrs;
139 uint8_t outerAttrs;
140 bool shareable;
141 uint32_t attributes; // Memory attributes formatted for PAR
142
143
144 // Access permissions
145 bool xn; // Execute Never
146 uint8_t ap:3; // Access permissions bits
147 uint8_t domain:4; // Access Domain
148
149 TlbRange range; // For fast TLB searching
150
151 //Construct an entry that maps to physical address addr for SE mode
152 TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
153 {
154 pfn = _paddr >> PageShift;
155 size = PageBytes - 1;
156 asid = _asn;
157 global = false;
158 valid = true;

--- 32 unchanged lines hidden (view full) ---

191 }
192
193 Addr
194 pAddr(Addr va)
195 {
196 return (pfn << N) | (va & size);
197 }
198
199 void serialize(std::ostream &os) { panic("Need to Implement\n"); }
200 void unserialize(Checkpoint *cp, const std::string &section)
201 { panic("Need to Implement\n");}
202};
203
204
205
206};
207#endif // __ARCH_ARM_PAGETABLE_H__
208