1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31#include "arch/arm/isa_traits.hh" 32#include "arch/arm/miscregs.hh" 33#include "arch/arm/nativetrace.hh" 34#include "cpu/thread_context.hh" 35#include "params/ArmNativeTrace.hh" 36 37namespace Trace { 38 |
39#if TRACING_ON |
40static const char *regNames[] = { 41 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 42 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", 43 "cpsr" 44}; |
45#endif |
46 47void |
48Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent) |
49{ |
50 oldState = state[current]; 51 current = (current + 1) % 2; 52 newState = state[current]; |
53 |
54 parent->read(newState, sizeof(newState[0]) * STATE_NUMVALS); 55 for (int i = 0; i < STATE_NUMVALS; i++) { 56 newState[i] = ArmISA::gtoh(newState[i]); 57 changed[i] = (oldState[i] != newState[i]); 58 } 59} |
60 |
61void 62Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) 63{ 64 oldState = state[current]; 65 current = (current + 1) % 2; 66 newState = state[current]; 67 |
68 // Regular int regs 69 for (int i = 0; i < 15; i++) { |
70 newState[i] = tc->readIntReg(i); 71 changed[i] = (oldState[i] != newState[i]); |
72 } 73 74 //R15, aliased with the PC |
75 newState[STATE_PC] = tc->readNextPC(); 76 changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]); |
77 78 //CPSR |
79 newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR); 80 changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); |
81} 82 |
83void 84Trace::ArmNativeTrace::check(NativeTraceRecord *record) 85{ 86 nState.update(this); 87 mState.update(record->getThread()); 88 89 // Regular int regs 90 for (int i = 0; i < STATE_NUMVALS; i++) { 91 if (nState.changed[i] || mState.changed[i]) { 92 const char *vergence = " "; 93 if (mState.oldState[i] == nState.oldState[i] && 94 mState.newState[i] != nState.newState[i]) { 95 vergence = "<>"; 96 } else if (mState.oldState[i] != nState.oldState[i] && 97 mState.newState[i] == nState.newState[i]) { 98 vergence = "><"; 99 } 100 if (!nState.changed[i]) { 101 DPRINTF(ExecRegDelta, "%s [%5s] "\ 102 "Native: %#010x "\ 103 "M5: %#010x => %#010x\n", 104 vergence, regNames[i], 105 nState.newState[i], 106 mState.oldState[i], mState.newState[i]); 107 } else if (!mState.changed[i]) { 108 DPRINTF(ExecRegDelta, "%s [%5s] "\ 109 "Native: %#010x => %#010x "\ 110 "M5: %#010x \n", 111 vergence, regNames[i], 112 nState.oldState[i], nState.newState[i], 113 mState.newState[i]); 114 } else if (mState.oldState[i] != nState.oldState[i] || 115 mState.newState[i] != nState.newState[i]) { 116 DPRINTF(ExecRegDelta, "%s [%5s] "\ 117 "Native: %#010x => %#010x "\ 118 "M5: %#010x => %#010x\n", 119 vergence, regNames[i], 120 nState.oldState[i], nState.newState[i], 121 mState.oldState[i], mState.newState[i]); 122 } 123 } 124 } 125} 126 |
127} /* namespace Trace */ 128 129//////////////////////////////////////////////////////////////////////// 130// 131// ExeTracer Simulation Object 132// 133Trace::ArmNativeTrace * 134ArmNativeTraceParams::create() 135{ 136 return new Trace::ArmNativeTrace(this); 137}; |