38a39
> #if TRACING_ON
43a45
> #endif
46c48
< Trace::ArmNativeTrace::check(NativeTraceRecord *record)
---
> Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
48c50,52
< ThreadContext *tc = record->getThread();
---
> oldState = state[current];
> current = (current + 1) % 2;
> newState = state[current];
50c54,59
< uint32_t regVal, realRegVal;
---
> parent->read(newState, sizeof(newState[0]) * STATE_NUMVALS);
> for (int i = 0; i < STATE_NUMVALS; i++) {
> newState[i] = ArmISA::gtoh(newState[i]);
> changed[i] = (oldState[i] != newState[i]);
> }
> }
52c61,67
< const char **regName = regNames;
---
> void
> Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
> {
> oldState = state[current];
> current = (current + 1) % 2;
> newState = state[current];
>
55,58c70,71
< regVal = tc->readIntReg(i);
< read(&realRegVal, sizeof(realRegVal));
< realRegVal = ArmISA::gtoh(realRegVal);
< checkReg(*(regName++), regVal, realRegVal);
---
> newState[i] = tc->readIntReg(i);
> changed[i] = (oldState[i] != newState[i]);
62,65c75,76
< regVal = tc->readNextPC();
< read(&realRegVal, sizeof(realRegVal));
< realRegVal = ArmISA::gtoh(realRegVal);
< checkReg(*(regName++), regVal, realRegVal);
---
> newState[STATE_PC] = tc->readNextPC();
> changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
68,71c79,80
< regVal = tc->readMiscReg(MISCREG_CPSR);
< read(&realRegVal, sizeof(realRegVal));
< realRegVal = ArmISA::gtoh(realRegVal);
< checkReg(*(regName++), regVal, realRegVal);
---
> newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR);
> changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
73a83,126
> void
> Trace::ArmNativeTrace::check(NativeTraceRecord *record)
> {
> nState.update(this);
> mState.update(record->getThread());
>
> // Regular int regs
> for (int i = 0; i < STATE_NUMVALS; i++) {
> if (nState.changed[i] || mState.changed[i]) {
> const char *vergence = " ";
> if (mState.oldState[i] == nState.oldState[i] &&
> mState.newState[i] != nState.newState[i]) {
> vergence = "<>";
> } else if (mState.oldState[i] != nState.oldState[i] &&
> mState.newState[i] == nState.newState[i]) {
> vergence = "><";
> }
> if (!nState.changed[i]) {
> DPRINTF(ExecRegDelta, "%s [%5s] "\
> "Native: %#010x "\
> "M5: %#010x => %#010x\n",
> vergence, regNames[i],
> nState.newState[i],
> mState.oldState[i], mState.newState[i]);
> } else if (!mState.changed[i]) {
> DPRINTF(ExecRegDelta, "%s [%5s] "\
> "Native: %#010x => %#010x "\
> "M5: %#010x \n",
> vergence, regNames[i],
> nState.oldState[i], nState.newState[i],
> mState.newState[i]);
> } else if (mState.oldState[i] != nState.oldState[i] ||
> mState.newState[i] != nState.newState[i]) {
> DPRINTF(ExecRegDelta, "%s [%5s] "\
> "Native: %#010x => %#010x "\
> "M5: %#010x => %#010x\n",
> vergence, regNames[i],
> nState.oldState[i], nState.newState[i],
> mState.oldState[i], mState.newState[i]);
> }
> }
> }
> }
>