1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/arm/isa_traits.hh"
44#include "arch/arm/miscregs.hh"
45#include "arch/arm/nativetrace.hh"
46#include "cpu/thread_context.hh"
47#include "debug/ExecRegDelta.hh"
48#include "params/ArmNativeTrace.hh"
49#include "sim/byteswap.hh"
50
51namespace Trace {
52
53#if TRACING_ON
54static const char *regNames[] = {
55 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
56 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/arm/isa_traits.hh"
44#include "arch/arm/miscregs.hh"
45#include "arch/arm/nativetrace.hh"
46#include "cpu/thread_context.hh"
47#include "debug/ExecRegDelta.hh"
48#include "params/ArmNativeTrace.hh"
49#include "sim/byteswap.hh"
50
51namespace Trace {
52
53#if TRACING_ON
54static const char *regNames[] = {
55 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
56 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
|
57 "cpsr"
| 57 "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
58 "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
59 "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
60 "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
61 "f31", "fpscr"
|
58};
59#endif
60
61void
62Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
63{
64 oldState = state[current];
65 current = (current + 1) % 2;
66 newState = state[current];
67
68 memcpy(newState, oldState, sizeof(state[0]));
69
| 62};
63#endif
64
65void
66Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
67{
68 oldState = state[current];
69 current = (current + 1) % 2;
70 newState = state[current];
71
72 memcpy(newState, oldState, sizeof(state[0]));
73
|
70 uint32_t diffVector;
| 74 uint64_t diffVector;
|
71 parent->read(&diffVector, sizeof(diffVector));
72 diffVector = ArmISA::gtoh(diffVector);
73
74 int changes = 0;
75 for (int i = 0; i < STATE_NUMVALS; i++) {
76 if (diffVector & 0x1) {
77 changed[i] = true;
78 changes++;
79 } else {
80 changed[i] = false;
81 }
82 diffVector >>= 1;
83 }
84
| 75 parent->read(&diffVector, sizeof(diffVector));
76 diffVector = ArmISA::gtoh(diffVector);
77
78 int changes = 0;
79 for (int i = 0; i < STATE_NUMVALS; i++) {
80 if (diffVector & 0x1) {
81 changed[i] = true;
82 changes++;
83 } else {
84 changed[i] = false;
85 }
86 diffVector >>= 1;
87 }
88
|
85 uint32_t values[changes];
| 89 uint64_t values[changes];
|
86 parent->read(values, sizeof(values));
87 int pos = 0;
88 for (int i = 0; i < STATE_NUMVALS; i++) {
89 if (changed[i]) {
90 newState[i] = ArmISA::gtoh(values[pos++]);
91 changed[i] = (newState[i] != oldState[i]);
92 }
93 }
94}
95
96void
97Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
98{
99 oldState = state[current];
100 current = (current + 1) % 2;
101 newState = state[current];
102
103 // Regular int regs
104 for (int i = 0; i < 15; i++) {
105 newState[i] = tc->readIntReg(i);
106 changed[i] = (oldState[i] != newState[i]);
107 }
108
109 //R15, aliased with the PC
110 newState[STATE_PC] = tc->pcState().npc();
111 changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
112
113 //CPSR
114 newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) |
115 tc->readIntReg(INTREG_CONDCODES);
116 changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
| 90 parent->read(values, sizeof(values));
91 int pos = 0;
92 for (int i = 0; i < STATE_NUMVALS; i++) {
93 if (changed[i]) {
94 newState[i] = ArmISA::gtoh(values[pos++]);
95 changed[i] = (newState[i] != oldState[i]);
96 }
97 }
98}
99
100void
101Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
102{
103 oldState = state[current];
104 current = (current + 1) % 2;
105 newState = state[current];
106
107 // Regular int regs
108 for (int i = 0; i < 15; i++) {
109 newState[i] = tc->readIntReg(i);
110 changed[i] = (oldState[i] != newState[i]);
111 }
112
113 //R15, aliased with the PC
114 newState[STATE_PC] = tc->pcState().npc();
115 changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
116
117 //CPSR
118 newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) |
119 tc->readIntReg(INTREG_CONDCODES);
120 changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
|
| 121
122 for (int i = 0; i < NumFloatArchRegs; i += 2) {
123 newState[STATE_F0 + (i >> 1)] =
124 static_cast<uint64_t>(tc->readFloatRegBits(i + 1)) << 32 |
125 tc->readFloatRegBits(i);
126 }
127 newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
128 tc->readIntReg(INTREG_FPCONDCODES);
|
117}
118
119void
120Trace::ArmNativeTrace::check(NativeTraceRecord *record)
121{
122 ThreadContext *tc = record->getThread();
123 // This area is read only on the target. It can't stop there to tell us
124 // what's going on, so we should skip over anything there also.
125 if (tc->nextInstAddr() > 0xffff0000)
126 return;
127 nState.update(this);
128 mState.update(tc);
129
130 // If a syscall just happened native trace needs another tick
131 if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
132 (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
133 DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
134 nState.update(this);
135
136 }
137
138 bool errorFound = false;
139 // Regular int regs
140 for (int i = 0; i < STATE_NUMVALS; i++) {
141 if (nState.changed[i] || mState.changed[i]) {
142 const char *vergence = " ";
143 bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
144 bool newMatch = (mState.newState[i] == nState.newState[i]);
145 if (oldMatch && newMatch) {
146 // The more things change, the more they stay the same.
147 continue;
148 } else if (oldMatch && !newMatch) {
149 vergence = "<>";
150 } else if (!oldMatch && newMatch) {
151 vergence = "><";
152 }
153 errorFound = true;
154 if (!nState.changed[i]) {
155 DPRINTF(ExecRegDelta, "%s [%5s] "\
156 "Native: %#010x "\
157 "M5: %#010x => %#010x\n",
158 vergence, regNames[i],
159 nState.newState[i],
160 mState.oldState[i], mState.newState[i]);
161 } else if (!mState.changed[i]) {
162 DPRINTF(ExecRegDelta, "%s [%5s] "\
163 "Native: %#010x => %#010x "\
164 "M5: %#010x \n",
165 vergence, regNames[i],
166 nState.oldState[i], nState.newState[i],
167 mState.newState[i]);
168 } else {
169 DPRINTF(ExecRegDelta, "%s [%5s] "\
170 "Native: %#010x => %#010x "\
171 "M5: %#010x => %#010x\n",
172 vergence, regNames[i],
173 nState.oldState[i], nState.newState[i],
174 mState.oldState[i], mState.newState[i]);
175 }
176 }
177 }
178 if (errorFound) {
179 StaticInstPtr inst = record->getStaticInst();
180 assert(inst);
181 bool ran = true;
182 if (inst->isMicroop()) {
183 ran = false;
184 inst = record->getMacroStaticInst();
185 }
186 assert(inst);
187 record->traceInst(inst, ran);
188
189 bool pcError = (mState.newState[STATE_PC] !=
190 nState.newState[STATE_PC]);
191 if (stopOnPCError && pcError)
192 panic("Native trace detected an error in control flow!");
193 }
194}
195
196} // namespace Trace
197
198////////////////////////////////////////////////////////////////////////
199//
200// ExeTracer Simulation Object
201//
202Trace::ArmNativeTrace *
203ArmNativeTraceParams::create()
204{
205 return new Trace::ArmNativeTrace(this);
206};
| 129}
130
131void
132Trace::ArmNativeTrace::check(NativeTraceRecord *record)
133{
134 ThreadContext *tc = record->getThread();
135 // This area is read only on the target. It can't stop there to tell us
136 // what's going on, so we should skip over anything there also.
137 if (tc->nextInstAddr() > 0xffff0000)
138 return;
139 nState.update(this);
140 mState.update(tc);
141
142 // If a syscall just happened native trace needs another tick
143 if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
144 (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
145 DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
146 nState.update(this);
147
148 }
149
150 bool errorFound = false;
151 // Regular int regs
152 for (int i = 0; i < STATE_NUMVALS; i++) {
153 if (nState.changed[i] || mState.changed[i]) {
154 const char *vergence = " ";
155 bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
156 bool newMatch = (mState.newState[i] == nState.newState[i]);
157 if (oldMatch && newMatch) {
158 // The more things change, the more they stay the same.
159 continue;
160 } else if (oldMatch && !newMatch) {
161 vergence = "<>";
162 } else if (!oldMatch && newMatch) {
163 vergence = "><";
164 }
165 errorFound = true;
166 if (!nState.changed[i]) {
167 DPRINTF(ExecRegDelta, "%s [%5s] "\
168 "Native: %#010x "\
169 "M5: %#010x => %#010x\n",
170 vergence, regNames[i],
171 nState.newState[i],
172 mState.oldState[i], mState.newState[i]);
173 } else if (!mState.changed[i]) {
174 DPRINTF(ExecRegDelta, "%s [%5s] "\
175 "Native: %#010x => %#010x "\
176 "M5: %#010x \n",
177 vergence, regNames[i],
178 nState.oldState[i], nState.newState[i],
179 mState.newState[i]);
180 } else {
181 DPRINTF(ExecRegDelta, "%s [%5s] "\
182 "Native: %#010x => %#010x "\
183 "M5: %#010x => %#010x\n",
184 vergence, regNames[i],
185 nState.oldState[i], nState.newState[i],
186 mState.oldState[i], mState.newState[i]);
187 }
188 }
189 }
190 if (errorFound) {
191 StaticInstPtr inst = record->getStaticInst();
192 assert(inst);
193 bool ran = true;
194 if (inst->isMicroop()) {
195 ran = false;
196 inst = record->getMacroStaticInst();
197 }
198 assert(inst);
199 record->traceInst(inst, ran);
200
201 bool pcError = (mState.newState[STATE_PC] !=
202 nState.newState[STATE_PC]);
203 if (stopOnPCError && pcError)
204 panic("Native trace detected an error in control flow!");
205 }
206}
207
208} // namespace Trace
209
210////////////////////////////////////////////////////////////////////////
211//
212// ExeTracer Simulation Object
213//
214Trace::ArmNativeTrace *
215ArmNativeTraceParams::create()
216{
217 return new Trace::ArmNativeTrace(this);
218};
|