1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/arm/isa_traits.hh" 32#include "arch/arm/miscregs.hh" 33#include "arch/arm/nativetrace.hh" 34#include "cpu/thread_context.hh" 35#include "params/ArmNativeTrace.hh" 36 37namespace Trace { 38
| 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/arm/isa_traits.hh" 32#include "arch/arm/miscregs.hh" 33#include "arch/arm/nativetrace.hh" 34#include "cpu/thread_context.hh" 35#include "params/ArmNativeTrace.hh" 36 37namespace Trace { 38
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| 39#if TRACING_ON
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39static const char *regNames[] = { 40 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 41 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", 42 "cpsr" 43};
| 40static const char *regNames[] = { 41 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 42 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", 43 "cpsr" 44};
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| 45#endif
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44 45void
| 46 47void
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46Trace::ArmNativeTrace::check(NativeTraceRecord *record)
| 48Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
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47{
| 49{
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48 ThreadContext *tc = record->getThread();
| 50 oldState = state[current]; 51 current = (current + 1) % 2; 52 newState = state[current];
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49
| 53
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50 uint32_t regVal, realRegVal;
| 54 parent->read(newState, sizeof(newState[0]) * STATE_NUMVALS); 55 for (int i = 0; i < STATE_NUMVALS; i++) { 56 newState[i] = ArmISA::gtoh(newState[i]); 57 changed[i] = (oldState[i] != newState[i]); 58 } 59}
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51
| 60
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52 const char **regName = regNames;
| 61void 62Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) 63{ 64 oldState = state[current]; 65 current = (current + 1) % 2; 66 newState = state[current]; 67
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53 // Regular int regs 54 for (int i = 0; i < 15; i++) {
| 68 // Regular int regs 69 for (int i = 0; i < 15; i++) {
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55 regVal = tc->readIntReg(i); 56 read(&realRegVal, sizeof(realRegVal)); 57 realRegVal = ArmISA::gtoh(realRegVal); 58 checkReg(*(regName++), regVal, realRegVal);
| 70 newState[i] = tc->readIntReg(i); 71 changed[i] = (oldState[i] != newState[i]);
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59 } 60 61 //R15, aliased with the PC
| 72 } 73 74 //R15, aliased with the PC
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62 regVal = tc->readNextPC(); 63 read(&realRegVal, sizeof(realRegVal)); 64 realRegVal = ArmISA::gtoh(realRegVal); 65 checkReg(*(regName++), regVal, realRegVal);
| 75 newState[STATE_PC] = tc->readNextPC(); 76 changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
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66 67 //CPSR
| 77 78 //CPSR
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68 regVal = tc->readMiscReg(MISCREG_CPSR); 69 read(&realRegVal, sizeof(realRegVal)); 70 realRegVal = ArmISA::gtoh(realRegVal); 71 checkReg(*(regName++), regVal, realRegVal);
| 79 newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR); 80 changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
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72} 73
| 81} 82
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| 83void 84Trace::ArmNativeTrace::check(NativeTraceRecord *record) 85{ 86 nState.update(this); 87 mState.update(record->getThread()); 88 89 // Regular int regs 90 for (int i = 0; i < STATE_NUMVALS; i++) { 91 if (nState.changed[i] || mState.changed[i]) { 92 const char *vergence = " "; 93 if (mState.oldState[i] == nState.oldState[i] && 94 mState.newState[i] != nState.newState[i]) { 95 vergence = "<>"; 96 } else if (mState.oldState[i] != nState.oldState[i] && 97 mState.newState[i] == nState.newState[i]) { 98 vergence = "><"; 99 } 100 if (!nState.changed[i]) { 101 DPRINTF(ExecRegDelta, "%s [%5s] "\ 102 "Native: %#010x "\ 103 "M5: %#010x => %#010x\n", 104 vergence, regNames[i], 105 nState.newState[i], 106 mState.oldState[i], mState.newState[i]); 107 } else if (!mState.changed[i]) { 108 DPRINTF(ExecRegDelta, "%s [%5s] "\ 109 "Native: %#010x => %#010x "\ 110 "M5: %#010x \n", 111 vergence, regNames[i], 112 nState.oldState[i], nState.newState[i], 113 mState.newState[i]); 114 } else if (mState.oldState[i] != nState.oldState[i] || 115 mState.newState[i] != nState.newState[i]) { 116 DPRINTF(ExecRegDelta, "%s [%5s] "\ 117 "Native: %#010x => %#010x "\ 118 "M5: %#010x => %#010x\n", 119 vergence, regNames[i], 120 nState.oldState[i], nState.newState[i], 121 mState.oldState[i], mState.newState[i]); 122 } 123 } 124 } 125} 126
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74} /* namespace Trace */ 75 76//////////////////////////////////////////////////////////////////////// 77// 78// ExeTracer Simulation Object 79// 80Trace::ArmNativeTrace * 81ArmNativeTraceParams::create() 82{ 83 return new Trace::ArmNativeTrace(this); 84};
| 127} /* namespace Trace */ 128 129//////////////////////////////////////////////////////////////////////// 130// 131// ExeTracer Simulation Object 132// 133Trace::ArmNativeTrace * 134ArmNativeTraceParams::create() 135{ 136 return new Trace::ArmNativeTrace(this); 137};
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