1/*
2 * Copyright (c) 2010-2011, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/arm/nativetrace.hh"
44
45#include "arch/arm/isa_traits.hh"
46#include "arch/arm/miscregs.hh"
47#include "cpu/thread_context.hh"
48#include "debug/ExecRegDelta.hh"
49#include "params/ArmNativeTrace.hh"
50#include "sim/byteswap.hh"
51
52namespace Trace {
53
54#if TRACING_ON
55static const char *regNames[] = {
56 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
57 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
58 "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
59 "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
60 "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
61 "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
62 "f31", "fpscr"
63};
64#endif
65
66void
67Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
68{
69 oldState = state[current];
70 current = (current + 1) % 2;
71 newState = state[current];
72
73 memcpy(newState, oldState, sizeof(state[0]));
74
75 uint64_t diffVector;
76 parent->read(&diffVector, sizeof(diffVector));
77 diffVector = ArmISA::gtoh(diffVector);
78
79 int changes = 0;
80 for (int i = 0; i < STATE_NUMVALS; i++) {
81 if (diffVector & 0x1) {
82 changed[i] = true;
83 changes++;
84 } else {
85 changed[i] = false;
86 }
87 diffVector >>= 1;
88 }
89
90 uint64_t values[changes];
91 parent->read(values, sizeof(values));
92 int pos = 0;
93 for (int i = 0; i < STATE_NUMVALS; i++) {
94 if (changed[i]) {
95 newState[i] = ArmISA::gtoh(values[pos++]);
96 changed[i] = (newState[i] != oldState[i]);
97 }
98 }
99}
100
101void
102Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
103{
104 oldState = state[current];
105 current = (current + 1) % 2;
106 newState = state[current];
107
108 // Regular int regs
109 for (int i = 0; i < 15; i++) {
110 newState[i] = tc->readIntReg(i);
111 changed[i] = (oldState[i] != newState[i]);
112 }
113
114 //R15, aliased with the PC
115 newState[STATE_PC] = tc->pcState().npc();
116 changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
117
118 //CPSR
119 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
120 cpsr.nz = tc->readCCReg(CCREG_NZ);
121 cpsr.c = tc->readCCReg(CCREG_C);
122 cpsr.v = tc->readCCReg(CCREG_V);
123 cpsr.ge = tc->readCCReg(CCREG_GE);
124
125 newState[STATE_CPSR] = cpsr;
126 changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
127
128 for (int i = 0; i < NumFloatV7ArchRegs; i += 2) {
129 newState[STATE_F0 + (i >> 1)] =
130 static_cast<uint64_t>(tc->readFloatRegBits(i + 1)) << 32 |
131 tc->readFloatRegBits(i);
132 }
133 newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
134 tc->readCCReg(CCREG_FP);
135}
136
137void
138Trace::ArmNativeTrace::check(NativeTraceRecord *record)
139{
140 ThreadContext *tc = record->getThread();
141 // This area is read only on the target. It can't stop there to tell us
142 // what's going on, so we should skip over anything there also.
143 if (tc->nextInstAddr() > 0xffff0000)
144 return;
145 nState.update(this);
146 mState.update(tc);
147
148 // If a syscall just happened native trace needs another tick
149 if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
150 (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
151 DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
152 nState.update(this);
153
154 }
155
156 bool errorFound = false;
157 // Regular int regs
158 for (int i = 0; i < STATE_NUMVALS; i++) {
159 if (nState.changed[i] || mState.changed[i]) {
160 bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
161 bool newMatch = (mState.newState[i] == nState.newState[i]);
162 if (oldMatch && newMatch) {
163 // The more things change, the more they stay the same.
164 continue;
165 }
166
167 errorFound = true;
168
169#ifndef NDEBUG
170 const char *vergence = " ";
171 if (oldMatch && !newMatch) {
172 vergence = "<>";
173 } else if (!oldMatch && newMatch) {
174 vergence = "><";
175 }
176
177 if (!nState.changed[i]) {
178 DPRINTF(ExecRegDelta, "%s [%5s] "\
179 "Native: %#010x "\
180 "M5: %#010x => %#010x\n",
181 vergence, regNames[i],
182 nState.newState[i],
183 mState.oldState[i], mState.newState[i]);
184 } else if (!mState.changed[i]) {
185 DPRINTF(ExecRegDelta, "%s [%5s] "\
186 "Native: %#010x => %#010x "\
187 "M5: %#010x \n",
188 vergence, regNames[i],
189 nState.oldState[i], nState.newState[i],
190 mState.newState[i]);
191 } else {
192 DPRINTF(ExecRegDelta, "%s [%5s] "\
193 "Native: %#010x => %#010x "\
194 "M5: %#010x => %#010x\n",
195 vergence, regNames[i],
196 nState.oldState[i], nState.newState[i],
197 mState.oldState[i], mState.newState[i]);
198 }
199#endif
200 }
201 }
202 if (errorFound) {
203 StaticInstPtr inst = record->getStaticInst();
204 assert(inst);
205 bool ran = true;
206 if (inst->isMicroop()) {
207 ran = false;
208 inst = record->getMacroStaticInst();
209 }
210 assert(inst);
211 record->traceInst(inst, ran);
212
213 bool pcError = (mState.newState[STATE_PC] !=
214 nState.newState[STATE_PC]);
215 if (stopOnPCError && pcError)
216 panic("Native trace detected an error in control flow!");
217 }
218}
219
220} // namespace Trace
221
222////////////////////////////////////////////////////////////////////////
223//
224// ExeTracer Simulation Object
225//
226Trace::ArmNativeTrace *
227ArmNativeTraceParams::create()
228{
229 return new Trace::ArmNativeTrace(this);
230}