mmapped_ipr.hh (9180:ee8d7a51651d) mmapped_ipr.hh (9897:e105fbf799e7)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 25 unchanged lines hidden (view full) ---

34#define __ARCH_ARM_MMAPPED_IPR_HH__
35
36/**
37 * @file
38 *
39 * ISA-specific helper functions for memory mapped IPR accesses.
40 */
41
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 25 unchanged lines hidden (view full) ---

34#define __ARCH_ARM_MMAPPED_IPR_HH__
35
36/**
37 * @file
38 *
39 * ISA-specific helper functions for memory mapped IPR accesses.
40 */
41
42#include "base/misc.hh"
43#include "mem/packet.hh"
42#include "arch/generic/mmapped_ipr.hh"
44
45class ThreadContext;
46
47namespace ArmISA
48{
43
44class ThreadContext;
45
46namespace ArmISA
47{
49inline Cycles
50handleIprRead(ThreadContext *xc, Packet *pkt)
51{
52 panic("No implementation for handleIprRead in ARM\n");
53}
54
55inline Cycles
56handleIprWrite(ThreadContext *xc, Packet *pkt)
57{
58 panic("No implementation for handleIprWrite in ARM\n");
59}
60
61
48 using GenericISA::handleIprRead;
49 using GenericISA::handleIprWrite;
62} // namespace ArmISA
63
64#endif
50} // namespace ArmISA
51
52#endif