miscregs_types.hh (13118:897ff5214d07) miscregs_types.hh (13394:ebe487b6f18a)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 305 unchanged lines hidden (view full) ---

314 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
315 Bitfield<29> afe; // Access flag enable (AArch32 only)
316 Bitfield<28> tre; // TEX remap enable (AArch32 only)
317 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
318 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
319 // DC CVAC and IC IVAU instructions
320 // (AArch64 SCTLR_EL1 only)
321 Bitfield<25> ee; // Exception Endianness
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 305 unchanged lines hidden (view full) ---

314 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
315 Bitfield<29> afe; // Access flag enable (AArch32 only)
316 Bitfield<28> tre; // TEX remap enable (AArch32 only)
317 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
318 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
319 // DC CVAC and IC IVAU instructions
320 // (AArch64 SCTLR_EL1 only)
321 Bitfield<25> ee; // Exception Endianness
322 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
323 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
324 // (AArch64 SCTLR_EL1 only)
325 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
326 Bitfield<22> u; // Alignment (dropped in ARMv7)
327 Bitfield<21> fi; // Fast interrupts configuration enable
328 // (ARMv7 only)
329 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
330 // (AArch32 only)

--- 305 unchanged lines hidden --- 		322 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
323 // (AArch64 SCTLR_EL1 only)
324 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
325 Bitfield<22> u; // Alignment (dropped in ARMv7)
326 Bitfield<21> fi; // Fast interrupts configuration enable
327 // (ARMv7 only)
328 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
329 // (AArch32 only)

--- 305 unchanged lines hidden ---