1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 * Giacomo Gabrielli
42 */
43
44#ifndef __ARCH_ARM_MISCREGS_TYPES_HH__
45#define __ARCH_ARM_MISCREGS_TYPES_HH__
46
47#include "base/bitunion.hh"
48
49namespace ArmISA
50{
51 BitUnion32(CPSR)
52 Bitfield<31, 30> nz;
53 Bitfield<29> c;
54 Bitfield<28> v;
55 Bitfield<27> q;
56 Bitfield<26, 25> it1;
57 Bitfield<24> j;
58 Bitfield<23, 22> res0_23_22;
59 Bitfield<21> ss; // AArch64
60 Bitfield<20> il; // AArch64
61 Bitfield<19, 16> ge;
62 Bitfield<15, 10> it2;
63 Bitfield<9> d; // AArch64
64 Bitfield<9> e;
65 Bitfield<8> a;
66 Bitfield<7> i;
67 Bitfield<6> f;
68 Bitfield<8, 6> aif;
69 Bitfield<9, 6> daif; // AArch64
70 Bitfield<5> t;
71 Bitfield<4> width; // AArch64
72 Bitfield<3, 2> el; // AArch64
73 Bitfield<4, 0> mode;
74 Bitfield<0> sp; // AArch64
75 EndBitUnion(CPSR)
76
77 BitUnion64(AA64DFR0)
78 Bitfield<43, 40> tracefilt;
79 Bitfield<39, 36> doublelock;
80 Bitfield<35, 32> pmsver;
81 Bitfield<31, 28> ctx_cmps;
82 Bitfield<23, 20> wrps;
83 Bitfield<15, 12> brps;
84 Bitfield<11, 8> pmuver;
85 Bitfield<7, 4> tracever;
86 Bitfield<3, 0> debugver;
87 EndBitUnion(AA64DFR0)
88
89 BitUnion64(AA64ISAR0)
90 Bitfield<63, 60> rndr;
91 Bitfield<59, 56> tlb;
92 Bitfield<55, 52> ts;
93 Bitfield<51, 48> fhm;
94 Bitfield<47, 44> dp;
95 Bitfield<43, 40> sm4;
96 Bitfield<39, 36> sm3;
97 Bitfield<35, 32> sha3;
98 Bitfield<31, 28> rdm;
99 Bitfield<23, 20> atomic;
100 Bitfield<19, 16> crc32;
101 Bitfield<15, 12> sha2;
102 Bitfield<11, 8> sha1;
103 Bitfield<3, 0> aes;
104 EndBitUnion(AA64ISAR0)
105
106 BitUnion64(AA64ISAR1)
107 Bitfield<43, 40> specres;
108 Bitfield<39, 36> sb;
109 Bitfield<35, 32> frintts;
110 Bitfield<31, 28> gpi;
111 Bitfield<27, 24> gpa;
112 Bitfield<23, 20> lrcpc;
113 Bitfield<19, 16> fcma;
114 Bitfield<15, 12> jscvt;
115 Bitfield<11, 8> api;
116 Bitfield<7, 4> apa;
117 Bitfield<3, 0> dpb;
118 EndBitUnion(AA64ISAR1)
119
120 BitUnion64(AA64MMFR0)
121 Bitfield<47, 44> exs;
122 Bitfield<43, 40> tgran4_2;
123 Bitfield<39, 36> tgran64_2;
124 Bitfield<35, 32> tgran16_2;
125 Bitfield<31, 28> tgran4;
126 Bitfield<27, 24> tgran64;
127 Bitfield<23, 20> tgran16;
128 Bitfield<19, 16> bigendEL0;
129 Bitfield<15, 12> snsmem;
130 Bitfield<11, 8> bigend;
131 Bitfield<7, 4> asidbits;
132 Bitfield<3, 0> parange;
133 EndBitUnion(AA64MMFR0)
134
135 BitUnion64(AA64MMFR1)
136 Bitfield<31, 28> xnx;
137 Bitfield<27, 24> specsei;
138 Bitfield<23, 20> pan;
139 Bitfield<19, 16> lo;
140 Bitfield<15, 12> hpds;
141 Bitfield<11, 8> vh;
142 Bitfield<7, 4> vmidbits;
143 Bitfield<3, 0> hafdbs;
144 EndBitUnion(AA64MMFR1)
145
146 BitUnion64(AA64MMFR2)
147 Bitfield<63, 60> e0pd;
148 Bitfield<59, 56> evt;
149 Bitfield<55, 52> bbm;
150 Bitfield<51, 48> ttl;
151 Bitfield<43, 40> fwb;
152 Bitfield<39, 36> ids;
153 Bitfield<35, 32> at;
154 Bitfield<31, 28> st;
155 Bitfield<27, 24> nv;
156 Bitfield<23, 20> ccidx;
157 Bitfield<19, 16> varange;
158 Bitfield<15, 12> iesb;
159 Bitfield<11, 8> lsm;
160 Bitfield<7, 4> uao;
161 Bitfield<3, 0> cnp;
162 EndBitUnion(AA64MMFR2)
163
164 BitUnion64(AA64PFR0)
165 Bitfield<63, 60> csv3;
166 Bitfield<59, 56> csv2;
167 Bitfield<51, 48> dit;
168 Bitfield<47, 44> amu;
169 Bitfield<43, 40> mpam;
170 Bitfield<39, 36> sel2;
171 Bitfield<35, 32> sve;
172 Bitfield<31, 28> ras;
173 Bitfield<27, 24> gic;
174 Bitfield<23, 20> advsimd;
175 Bitfield<19, 16> fp;
176 Bitfield<15, 12> el3;
177 Bitfield<11, 8> el2;
178 Bitfield<7, 4> el1;
179 Bitfield<3, 0> el0;
180 EndBitUnion(AA64PFR0)
181
182 BitUnion32(HDCR)
183 Bitfield<11> tdra;
184 Bitfield<10> tdosa;
185 Bitfield<9> tda;
186 Bitfield<8> tde;
187 Bitfield<7> hpme;
188 Bitfield<6> tpm;
189 Bitfield<5> tpmcr;
190 Bitfield<4, 0> hpmn;
191 EndBitUnion(HDCR)
192
193 BitUnion32(HCPTR)
194 Bitfield<31> tcpac;
195 Bitfield<20> tta;
196 Bitfield<15> tase;
197 Bitfield<13> tcp13;
198 Bitfield<12> tcp12;
199 Bitfield<11> tcp11;
200 Bitfield<10> tcp10;
201 Bitfield<10> tfp; // AArch64
202 Bitfield<9> tcp9;
203 Bitfield<8> tcp8;
| 1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 * Giacomo Gabrielli
42 */
43
44#ifndef __ARCH_ARM_MISCREGS_TYPES_HH__
45#define __ARCH_ARM_MISCREGS_TYPES_HH__
46
47#include "base/bitunion.hh"
48
49namespace ArmISA
50{
51 BitUnion32(CPSR)
52 Bitfield<31, 30> nz;
53 Bitfield<29> c;
54 Bitfield<28> v;
55 Bitfield<27> q;
56 Bitfield<26, 25> it1;
57 Bitfield<24> j;
58 Bitfield<23, 22> res0_23_22;
59 Bitfield<21> ss; // AArch64
60 Bitfield<20> il; // AArch64
61 Bitfield<19, 16> ge;
62 Bitfield<15, 10> it2;
63 Bitfield<9> d; // AArch64
64 Bitfield<9> e;
65 Bitfield<8> a;
66 Bitfield<7> i;
67 Bitfield<6> f;
68 Bitfield<8, 6> aif;
69 Bitfield<9, 6> daif; // AArch64
70 Bitfield<5> t;
71 Bitfield<4> width; // AArch64
72 Bitfield<3, 2> el; // AArch64
73 Bitfield<4, 0> mode;
74 Bitfield<0> sp; // AArch64
75 EndBitUnion(CPSR)
76
77 BitUnion64(AA64DFR0)
78 Bitfield<43, 40> tracefilt;
79 Bitfield<39, 36> doublelock;
80 Bitfield<35, 32> pmsver;
81 Bitfield<31, 28> ctx_cmps;
82 Bitfield<23, 20> wrps;
83 Bitfield<15, 12> brps;
84 Bitfield<11, 8> pmuver;
85 Bitfield<7, 4> tracever;
86 Bitfield<3, 0> debugver;
87 EndBitUnion(AA64DFR0)
88
89 BitUnion64(AA64ISAR0)
90 Bitfield<63, 60> rndr;
91 Bitfield<59, 56> tlb;
92 Bitfield<55, 52> ts;
93 Bitfield<51, 48> fhm;
94 Bitfield<47, 44> dp;
95 Bitfield<43, 40> sm4;
96 Bitfield<39, 36> sm3;
97 Bitfield<35, 32> sha3;
98 Bitfield<31, 28> rdm;
99 Bitfield<23, 20> atomic;
100 Bitfield<19, 16> crc32;
101 Bitfield<15, 12> sha2;
102 Bitfield<11, 8> sha1;
103 Bitfield<3, 0> aes;
104 EndBitUnion(AA64ISAR0)
105
106 BitUnion64(AA64ISAR1)
107 Bitfield<43, 40> specres;
108 Bitfield<39, 36> sb;
109 Bitfield<35, 32> frintts;
110 Bitfield<31, 28> gpi;
111 Bitfield<27, 24> gpa;
112 Bitfield<23, 20> lrcpc;
113 Bitfield<19, 16> fcma;
114 Bitfield<15, 12> jscvt;
115 Bitfield<11, 8> api;
116 Bitfield<7, 4> apa;
117 Bitfield<3, 0> dpb;
118 EndBitUnion(AA64ISAR1)
119
120 BitUnion64(AA64MMFR0)
121 Bitfield<47, 44> exs;
122 Bitfield<43, 40> tgran4_2;
123 Bitfield<39, 36> tgran64_2;
124 Bitfield<35, 32> tgran16_2;
125 Bitfield<31, 28> tgran4;
126 Bitfield<27, 24> tgran64;
127 Bitfield<23, 20> tgran16;
128 Bitfield<19, 16> bigendEL0;
129 Bitfield<15, 12> snsmem;
130 Bitfield<11, 8> bigend;
131 Bitfield<7, 4> asidbits;
132 Bitfield<3, 0> parange;
133 EndBitUnion(AA64MMFR0)
134
135 BitUnion64(AA64MMFR1)
136 Bitfield<31, 28> xnx;
137 Bitfield<27, 24> specsei;
138 Bitfield<23, 20> pan;
139 Bitfield<19, 16> lo;
140 Bitfield<15, 12> hpds;
141 Bitfield<11, 8> vh;
142 Bitfield<7, 4> vmidbits;
143 Bitfield<3, 0> hafdbs;
144 EndBitUnion(AA64MMFR1)
145
146 BitUnion64(AA64MMFR2)
147 Bitfield<63, 60> e0pd;
148 Bitfield<59, 56> evt;
149 Bitfield<55, 52> bbm;
150 Bitfield<51, 48> ttl;
151 Bitfield<43, 40> fwb;
152 Bitfield<39, 36> ids;
153 Bitfield<35, 32> at;
154 Bitfield<31, 28> st;
155 Bitfield<27, 24> nv;
156 Bitfield<23, 20> ccidx;
157 Bitfield<19, 16> varange;
158 Bitfield<15, 12> iesb;
159 Bitfield<11, 8> lsm;
160 Bitfield<7, 4> uao;
161 Bitfield<3, 0> cnp;
162 EndBitUnion(AA64MMFR2)
163
164 BitUnion64(AA64PFR0)
165 Bitfield<63, 60> csv3;
166 Bitfield<59, 56> csv2;
167 Bitfield<51, 48> dit;
168 Bitfield<47, 44> amu;
169 Bitfield<43, 40> mpam;
170 Bitfield<39, 36> sel2;
171 Bitfield<35, 32> sve;
172 Bitfield<31, 28> ras;
173 Bitfield<27, 24> gic;
174 Bitfield<23, 20> advsimd;
175 Bitfield<19, 16> fp;
176 Bitfield<15, 12> el3;
177 Bitfield<11, 8> el2;
178 Bitfield<7, 4> el1;
179 Bitfield<3, 0> el0;
180 EndBitUnion(AA64PFR0)
181
182 BitUnion32(HDCR)
183 Bitfield<11> tdra;
184 Bitfield<10> tdosa;
185 Bitfield<9> tda;
186 Bitfield<8> tde;
187 Bitfield<7> hpme;
188 Bitfield<6> tpm;
189 Bitfield<5> tpmcr;
190 Bitfield<4, 0> hpmn;
191 EndBitUnion(HDCR)
192
193 BitUnion32(HCPTR)
194 Bitfield<31> tcpac;
195 Bitfield<20> tta;
196 Bitfield<15> tase;
197 Bitfield<13> tcp13;
198 Bitfield<12> tcp12;
199 Bitfield<11> tcp11;
200 Bitfield<10> tcp10;
201 Bitfield<10> tfp; // AArch64
202 Bitfield<9> tcp9;
203 Bitfield<8> tcp8;
|
| 204 Bitfield<8> tz; // SVE
|
204 Bitfield<7> tcp7;
205 Bitfield<6> tcp6;
206 Bitfield<5> tcp5;
207 Bitfield<4> tcp4;
208 Bitfield<3> tcp3;
209 Bitfield<2> tcp2;
210 Bitfield<1> tcp1;
211 Bitfield<0> tcp0;
212 EndBitUnion(HCPTR)
213
214 BitUnion32(HSTR)
215 Bitfield<17> tjdbx;
216 Bitfield<16> ttee;
217 Bitfield<15> t15;
218 Bitfield<13> t13;
219 Bitfield<12> t12;
220 Bitfield<11> t11;
221 Bitfield<10> t10;
222 Bitfield<9> t9;
223 Bitfield<8> t8;
224 Bitfield<7> t7;
225 Bitfield<6> t6;
226 Bitfield<5> t5;
227 Bitfield<4> t4;
228 Bitfield<3> t3;
229 Bitfield<2> t2;
230 Bitfield<1> t1;
231 Bitfield<0> t0;
232 EndBitUnion(HSTR)
233
234 BitUnion64(HCR)
235 Bitfield<34> e2h; // AArch64
236 Bitfield<33> id; // AArch64
237 Bitfield<32> cd; // AArch64
238 Bitfield<31> rw; // AArch64
239 Bitfield<30> trvm; // AArch64
240 Bitfield<29> hcd; // AArch64
241 Bitfield<28> tdz; // AArch64
242
243 Bitfield<27> tge;
244 Bitfield<26> tvm;
245 Bitfield<25> ttlb;
246 Bitfield<24> tpu;
247 Bitfield<23> tpc;
248 Bitfield<22> tsw;
249 Bitfield<21> tac;
250 Bitfield<21> tacr; // AArch64
251 Bitfield<20> tidcp;
252 Bitfield<19> tsc;
253 Bitfield<18> tid3;
254 Bitfield<17> tid2;
255 Bitfield<16> tid1;
256 Bitfield<15> tid0;
257 Bitfield<14> twe;
258 Bitfield<13> twi;
259 Bitfield<12> dc;
260 Bitfield<11, 10> bsu;
261 Bitfield<9> fb;
262 Bitfield<8> va;
263 Bitfield<8> vse; // AArch64
264 Bitfield<7> vi;
265 Bitfield<6> vf;
266 Bitfield<5> amo;
267 Bitfield<4> imo;
268 Bitfield<3> fmo;
269 Bitfield<2> ptw;
270 Bitfield<1> swio;
271 Bitfield<0> vm;
272 EndBitUnion(HCR)
273
274 BitUnion32(NSACR)
275 Bitfield<20> nstrcdis;
276 Bitfield<19> rfr;
277 Bitfield<15> nsasedis;
278 Bitfield<14> nsd32dis;
279 Bitfield<13> cp13;
280 Bitfield<12> cp12;
281 Bitfield<11> cp11;
282 Bitfield<10> cp10;
283 Bitfield<9> cp9;
284 Bitfield<8> cp8;
285 Bitfield<7> cp7;
286 Bitfield<6> cp6;
287 Bitfield<5> cp5;
288 Bitfield<4> cp4;
289 Bitfield<3> cp3;
290 Bitfield<2> cp2;
291 Bitfield<1> cp1;
292 Bitfield<0> cp0;
293 EndBitUnion(NSACR)
294
295 BitUnion32(SCR)
296 Bitfield<13> twe;
297 Bitfield<12> twi;
298 Bitfield<11> st; // AArch64
299 Bitfield<10> rw; // AArch64
300 Bitfield<9> sif;
301 Bitfield<8> hce;
302 Bitfield<7> scd;
303 Bitfield<7> smd; // AArch64
304 Bitfield<6> nEt;
305 Bitfield<5> aw;
306 Bitfield<4> fw;
307 Bitfield<3> ea;
308 Bitfield<2> fiq;
309 Bitfield<1> irq;
310 Bitfield<0> ns;
311 EndBitUnion(SCR)
312
313 BitUnion32(SCTLR)
314 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
315 Bitfield<29> afe; // Access flag enable (AArch32 only)
316 Bitfield<28> tre; // TEX remap enable (AArch32 only)
317 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
318 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
319 // DC CVAC and IC IVAU instructions
320 // (AArch64 SCTLR_EL1 only)
321 Bitfield<25> ee; // Exception Endianness
322 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
323 // (AArch64 SCTLR_EL1 only)
324 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
325 Bitfield<22> u; // Alignment (dropped in ARMv7)
326 Bitfield<21> fi; // Fast interrupts configuration enable
327 // (ARMv7 only)
328 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
329 // (AArch32 only)
330 Bitfield<19> dz; // Divide by Zero fault enable
331 // (dropped in ARMv7)
332 Bitfield<19> wxn; // Write permission implies XN
333 Bitfield<18> ntwe; // Not trap WFE
334 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
335 Bitfield<18> rao2; // Read as one
336 Bitfield<16> ntwi; // Not trap WFI
337 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
338 Bitfield<16> rao3; // Read as one
339 Bitfield<15> uct; // Enable EL0 access to CTR_EL0
340 // (AArch64 SCTLR_EL1 only)
341 Bitfield<14> rr; // Round Robin select (ARMv7 only)
342 Bitfield<14> dze; // Enable EL0 access to DC ZVA
343 // (AArch64 SCTLR_EL1 only)
344 Bitfield<13> v; // Vectors bit (AArch32 only)
345 Bitfield<12> i; // Instruction cache enable
346 Bitfield<11> z; // Branch prediction enable (ARMv7 only)
347 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
348 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
349 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
350 Bitfield<8> sed; // SETEND disable
351 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
352 Bitfield<7> b; // Endianness support (dropped in ARMv7)
353 Bitfield<7> itd; // IT disable
354 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
355 Bitfield<6, 3> rao4; // Read as one
356 Bitfield<6> thee; // ThumbEE enable
357 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
358 Bitfield<5> cp15ben; // CP15 barrier enable
359 // (AArch32 and AArch64 SCTLR_EL1 only)
360 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
361 // (AArch64 SCTLR_EL1 only)
362 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
363 Bitfield<2> c; // Cache enable
364 Bitfield<1> a; // Alignment check enable
365 Bitfield<0> m; // MMU enable
366 EndBitUnion(SCTLR)
367
368 BitUnion32(CPACR)
369 Bitfield<1, 0> cp0;
370 Bitfield<3, 2> cp1;
371 Bitfield<5, 4> cp2;
372 Bitfield<7, 6> cp3;
373 Bitfield<9, 8> cp4;
374 Bitfield<11, 10> cp5;
375 Bitfield<13, 12> cp6;
376 Bitfield<15, 14> cp7;
377 Bitfield<17, 16> cp8;
| 205 Bitfield<7> tcp7;
206 Bitfield<6> tcp6;
207 Bitfield<5> tcp5;
208 Bitfield<4> tcp4;
209 Bitfield<3> tcp3;
210 Bitfield<2> tcp2;
211 Bitfield<1> tcp1;
212 Bitfield<0> tcp0;
213 EndBitUnion(HCPTR)
214
215 BitUnion32(HSTR)
216 Bitfield<17> tjdbx;
217 Bitfield<16> ttee;
218 Bitfield<15> t15;
219 Bitfield<13> t13;
220 Bitfield<12> t12;
221 Bitfield<11> t11;
222 Bitfield<10> t10;
223 Bitfield<9> t9;
224 Bitfield<8> t8;
225 Bitfield<7> t7;
226 Bitfield<6> t6;
227 Bitfield<5> t5;
228 Bitfield<4> t4;
229 Bitfield<3> t3;
230 Bitfield<2> t2;
231 Bitfield<1> t1;
232 Bitfield<0> t0;
233 EndBitUnion(HSTR)
234
235 BitUnion64(HCR)
236 Bitfield<34> e2h; // AArch64
237 Bitfield<33> id; // AArch64
238 Bitfield<32> cd; // AArch64
239 Bitfield<31> rw; // AArch64
240 Bitfield<30> trvm; // AArch64
241 Bitfield<29> hcd; // AArch64
242 Bitfield<28> tdz; // AArch64
243
244 Bitfield<27> tge;
245 Bitfield<26> tvm;
246 Bitfield<25> ttlb;
247 Bitfield<24> tpu;
248 Bitfield<23> tpc;
249 Bitfield<22> tsw;
250 Bitfield<21> tac;
251 Bitfield<21> tacr; // AArch64
252 Bitfield<20> tidcp;
253 Bitfield<19> tsc;
254 Bitfield<18> tid3;
255 Bitfield<17> tid2;
256 Bitfield<16> tid1;
257 Bitfield<15> tid0;
258 Bitfield<14> twe;
259 Bitfield<13> twi;
260 Bitfield<12> dc;
261 Bitfield<11, 10> bsu;
262 Bitfield<9> fb;
263 Bitfield<8> va;
264 Bitfield<8> vse; // AArch64
265 Bitfield<7> vi;
266 Bitfield<6> vf;
267 Bitfield<5> amo;
268 Bitfield<4> imo;
269 Bitfield<3> fmo;
270 Bitfield<2> ptw;
271 Bitfield<1> swio;
272 Bitfield<0> vm;
273 EndBitUnion(HCR)
274
275 BitUnion32(NSACR)
276 Bitfield<20> nstrcdis;
277 Bitfield<19> rfr;
278 Bitfield<15> nsasedis;
279 Bitfield<14> nsd32dis;
280 Bitfield<13> cp13;
281 Bitfield<12> cp12;
282 Bitfield<11> cp11;
283 Bitfield<10> cp10;
284 Bitfield<9> cp9;
285 Bitfield<8> cp8;
286 Bitfield<7> cp7;
287 Bitfield<6> cp6;
288 Bitfield<5> cp5;
289 Bitfield<4> cp4;
290 Bitfield<3> cp3;
291 Bitfield<2> cp2;
292 Bitfield<1> cp1;
293 Bitfield<0> cp0;
294 EndBitUnion(NSACR)
295
296 BitUnion32(SCR)
297 Bitfield<13> twe;
298 Bitfield<12> twi;
299 Bitfield<11> st; // AArch64
300 Bitfield<10> rw; // AArch64
301 Bitfield<9> sif;
302 Bitfield<8> hce;
303 Bitfield<7> scd;
304 Bitfield<7> smd; // AArch64
305 Bitfield<6> nEt;
306 Bitfield<5> aw;
307 Bitfield<4> fw;
308 Bitfield<3> ea;
309 Bitfield<2> fiq;
310 Bitfield<1> irq;
311 Bitfield<0> ns;
312 EndBitUnion(SCR)
313
314 BitUnion32(SCTLR)
315 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
316 Bitfield<29> afe; // Access flag enable (AArch32 only)
317 Bitfield<28> tre; // TEX remap enable (AArch32 only)
318 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
319 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
320 // DC CVAC and IC IVAU instructions
321 // (AArch64 SCTLR_EL1 only)
322 Bitfield<25> ee; // Exception Endianness
323 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
324 // (AArch64 SCTLR_EL1 only)
325 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
326 Bitfield<22> u; // Alignment (dropped in ARMv7)
327 Bitfield<21> fi; // Fast interrupts configuration enable
328 // (ARMv7 only)
329 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
330 // (AArch32 only)
331 Bitfield<19> dz; // Divide by Zero fault enable
332 // (dropped in ARMv7)
333 Bitfield<19> wxn; // Write permission implies XN
334 Bitfield<18> ntwe; // Not trap WFE
335 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
336 Bitfield<18> rao2; // Read as one
337 Bitfield<16> ntwi; // Not trap WFI
338 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
339 Bitfield<16> rao3; // Read as one
340 Bitfield<15> uct; // Enable EL0 access to CTR_EL0
341 // (AArch64 SCTLR_EL1 only)
342 Bitfield<14> rr; // Round Robin select (ARMv7 only)
343 Bitfield<14> dze; // Enable EL0 access to DC ZVA
344 // (AArch64 SCTLR_EL1 only)
345 Bitfield<13> v; // Vectors bit (AArch32 only)
346 Bitfield<12> i; // Instruction cache enable
347 Bitfield<11> z; // Branch prediction enable (ARMv7 only)
348 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
349 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
350 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
351 Bitfield<8> sed; // SETEND disable
352 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
353 Bitfield<7> b; // Endianness support (dropped in ARMv7)
354 Bitfield<7> itd; // IT disable
355 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
356 Bitfield<6, 3> rao4; // Read as one
357 Bitfield<6> thee; // ThumbEE enable
358 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
359 Bitfield<5> cp15ben; // CP15 barrier enable
360 // (AArch32 and AArch64 SCTLR_EL1 only)
361 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
362 // (AArch64 SCTLR_EL1 only)
363 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
364 Bitfield<2> c; // Cache enable
365 Bitfield<1> a; // Alignment check enable
366 Bitfield<0> m; // MMU enable
367 EndBitUnion(SCTLR)
368
369 BitUnion32(CPACR)
370 Bitfield<1, 0> cp0;
371 Bitfield<3, 2> cp1;
372 Bitfield<5, 4> cp2;
373 Bitfield<7, 6> cp3;
374 Bitfield<9, 8> cp4;
375 Bitfield<11, 10> cp5;
376 Bitfield<13, 12> cp6;
377 Bitfield<15, 14> cp7;
378 Bitfield<17, 16> cp8;
|
| 379 Bitfield<17, 16> zen; // SVE
|
378 Bitfield<19, 18> cp9;
379 Bitfield<21, 20> cp10;
380 Bitfield<21, 20> fpen; // AArch64
381 Bitfield<23, 22> cp11;
382 Bitfield<25, 24> cp12;
383 Bitfield<27, 26> cp13;
384 Bitfield<29, 28> rsvd;
385 Bitfield<28> tta; // AArch64
386 Bitfield<30> d32dis;
387 Bitfield<31> asedis;
388 EndBitUnion(CPACR)
389
390 BitUnion32(FSR)
391 Bitfield<3, 0> fsLow;
392 Bitfield<5, 0> status; // LPAE
393 Bitfield<7, 4> domain;
394 Bitfield<9> lpae;
395 Bitfield<10> fsHigh;
396 Bitfield<11> wnr;
397 Bitfield<12> ext;
398 Bitfield<13> cm; // LPAE
399 EndBitUnion(FSR)
400
401 BitUnion32(FPSCR)
402 Bitfield<0> ioc;
403 Bitfield<1> dzc;
404 Bitfield<2> ofc;
405 Bitfield<3> ufc;
406 Bitfield<4> ixc;
407 Bitfield<7> idc;
408 Bitfield<8> ioe;
409 Bitfield<9> dze;
410 Bitfield<10> ofe;
411 Bitfield<11> ufe;
412 Bitfield<12> ixe;
413 Bitfield<15> ide;
414 Bitfield<18, 16> len;
415 Bitfield<19> fz16;
416 Bitfield<21, 20> stride;
417 Bitfield<23, 22> rMode;
418 Bitfield<24> fz;
419 Bitfield<25> dn;
420 Bitfield<26> ahp;
421 Bitfield<27> qc;
422 Bitfield<28> v;
423 Bitfield<29> c;
424 Bitfield<30> z;
425 Bitfield<31> n;
426 EndBitUnion(FPSCR)
427
428 BitUnion32(FPEXC)
429 Bitfield<31> ex;
430 Bitfield<30> en;
431 Bitfield<29, 0> subArchDefined;
432 EndBitUnion(FPEXC)
433
434 BitUnion32(MVFR0)
435 Bitfield<3, 0> advSimdRegisters;
436 Bitfield<7, 4> singlePrecision;
437 Bitfield<11, 8> doublePrecision;
438 Bitfield<15, 12> vfpExceptionTrapping;
439 Bitfield<19, 16> divide;
440 Bitfield<23, 20> squareRoot;
441 Bitfield<27, 24> shortVectors;
442 Bitfield<31, 28> roundingModes;
443 EndBitUnion(MVFR0)
444
445 BitUnion32(MVFR1)
446 Bitfield<3, 0> flushToZero;
447 Bitfield<7, 4> defaultNaN;
448 Bitfield<11, 8> advSimdLoadStore;
449 Bitfield<15, 12> advSimdInteger;
450 Bitfield<19, 16> advSimdSinglePrecision;
451 Bitfield<23, 20> advSimdHalfPrecision;
452 Bitfield<27, 24> vfpHalfPrecision;
453 Bitfield<31, 28> raz;
454 EndBitUnion(MVFR1)
455
456 BitUnion64(TTBCR)
457 // Short-descriptor translation table format
458 Bitfield<2, 0> n;
459 Bitfield<4> pd0;
460 Bitfield<5> pd1;
461 // Long-descriptor translation table format
462 Bitfield<2, 0> t0sz;
463 Bitfield<6> t2e;
464 Bitfield<7> epd0;
465 Bitfield<9, 8> irgn0;
466 Bitfield<11, 10> orgn0;
467 Bitfield<13, 12> sh0;
468 Bitfield<14> tg0;
469 Bitfield<18, 16> t1sz;
470 Bitfield<22> a1;
471 Bitfield<23> epd1;
472 Bitfield<25, 24> irgn1;
473 Bitfield<27, 26> orgn1;
474 Bitfield<29, 28> sh1;
475 Bitfield<30> tg1;
476 Bitfield<34, 32> ips;
477 Bitfield<36> as;
478 Bitfield<37> tbi0;
479 Bitfield<38> tbi1;
480 // Common
481 Bitfield<31> eae;
482 // TCR_EL2/3 (AArch64)
483 Bitfield<18, 16> ps;
484 Bitfield<20> tbi;
485 Bitfield<41> hpd0;
486 Bitfield<42> hpd1;
487 EndBitUnion(TTBCR)
488
489 // Fields of TCR_EL{1,2,3} (mostly overlapping)
490 // TCR_EL1 is natively 64 bits, the others are 32 bits
491 BitUnion64(TCR)
492 Bitfield<5, 0> t0sz;
493 Bitfield<7> epd0; // EL1
494 Bitfield<9, 8> irgn0;
495 Bitfield<11, 10> orgn0;
496 Bitfield<13, 12> sh0;
497 Bitfield<15, 14> tg0;
498 Bitfield<18, 16> ps;
499 Bitfield<20> tbi; // EL2/EL3
500 Bitfield<21, 16> t1sz; // EL1
501 Bitfield<22> a1; // EL1
502 Bitfield<23> epd1; // EL1
503 Bitfield<25, 24> irgn1; // EL1
504 Bitfield<27, 26> orgn1; // EL1
505 Bitfield<29, 28> sh1; // EL1
506 Bitfield<31, 30> tg1; // EL1
507 Bitfield<34, 32> ips; // EL1
508 Bitfield<36> as; // EL1
509 Bitfield<37> tbi0; // EL1
510 Bitfield<38> tbi1; // EL1
511 Bitfield<39> ha;
512 Bitfield<40> hd;
513 Bitfield<41> hpd0;
514 Bitfield<42> hpd1;
515 EndBitUnion(TCR)
516
517 BitUnion32(HTCR)
518 Bitfield<2, 0> t0sz;
519 Bitfield<9, 8> irgn0;
520 Bitfield<11, 10> orgn0;
521 Bitfield<13, 12> sh0;
522 Bitfield<24> hpd;
523 EndBitUnion(HTCR)
524
525 BitUnion32(VTCR_t)
526 Bitfield<3, 0> t0sz;
527 Bitfield<4> s;
528 Bitfield<5, 0> t0sz64;
529 Bitfield<7, 6> sl0;
530 Bitfield<9, 8> irgn0;
531 Bitfield<11, 10> orgn0;
532 Bitfield<13, 12> sh0;
533 Bitfield<15, 14> tg0;
534 Bitfield<18, 16> ps; // Only defined for VTCR_EL2
535 Bitfield<21> ha; // Only defined for VTCR_EL2
536 Bitfield<22> hd; // Only defined for VTCR_EL2
537 EndBitUnion(VTCR_t)
538
539 BitUnion32(PRRR)
540 Bitfield<1,0> tr0;
541 Bitfield<3,2> tr1;
542 Bitfield<5,4> tr2;
543 Bitfield<7,6> tr3;
544 Bitfield<9,8> tr4;
545 Bitfield<11,10> tr5;
546 Bitfield<13,12> tr6;
547 Bitfield<15,14> tr7;
548 Bitfield<16> ds0;
549 Bitfield<17> ds1;
550 Bitfield<18> ns0;
551 Bitfield<19> ns1;
552 Bitfield<24> nos0;
553 Bitfield<25> nos1;
554 Bitfield<26> nos2;
555 Bitfield<27> nos3;
556 Bitfield<28> nos4;
557 Bitfield<29> nos5;
558 Bitfield<30> nos6;
559 Bitfield<31> nos7;
560 EndBitUnion(PRRR)
561
562 BitUnion32(NMRR)
563 Bitfield<1,0> ir0;
564 Bitfield<3,2> ir1;
565 Bitfield<5,4> ir2;
566 Bitfield<7,6> ir3;
567 Bitfield<9,8> ir4;
568 Bitfield<11,10> ir5;
569 Bitfield<13,12> ir6;
570 Bitfield<15,14> ir7;
571 Bitfield<17,16> or0;
572 Bitfield<19,18> or1;
573 Bitfield<21,20> or2;
574 Bitfield<23,22> or3;
575 Bitfield<25,24> or4;
576 Bitfield<27,26> or5;
577 Bitfield<29,28> or6;
578 Bitfield<31,30> or7;
579 EndBitUnion(NMRR)
580
581 BitUnion32(CONTEXTIDR)
582 Bitfield<7,0> asid;
583 Bitfield<31,8> procid;
584 EndBitUnion(CONTEXTIDR)
585
586 BitUnion32(L2CTLR)
587 Bitfield<2,0> sataRAMLatency;
588 Bitfield<4,3> reserved_4_3;
589 Bitfield<5> dataRAMSetup;
590 Bitfield<8,6> tagRAMLatency;
591 Bitfield<9> tagRAMSetup;
592 Bitfield<11,10> dataRAMSlice;
593 Bitfield<12> tagRAMSlice;
594 Bitfield<20,13> reserved_20_13;
595 Bitfield<21> eccandParityEnable;
596 Bitfield<22> reserved_22;
597 Bitfield<23> interptCtrlPresent;
598 Bitfield<25,24> numCPUs;
599 Bitfield<30,26> reserved_30_26;
600 Bitfield<31> l2rstDISABLE_monitor;
601 EndBitUnion(L2CTLR)
602
603 BitUnion32(CTR)
604 Bitfield<3,0> iCacheLineSize;
605 Bitfield<13,4> raz_13_4;
606 Bitfield<15,14> l1IndexPolicy;
607 Bitfield<19,16> dCacheLineSize;
608 Bitfield<23,20> erg;
609 Bitfield<27,24> cwg;
610 Bitfield<28> raz_28;
611 Bitfield<31,29> format;
612 EndBitUnion(CTR)
613
614 BitUnion32(PMSELR)
615 Bitfield<4, 0> sel;
616 EndBitUnion(PMSELR)
617
618 BitUnion64(PAR)
619 // 64-bit format
620 Bitfield<63, 56> attr;
621 Bitfield<39, 12> pa;
622 Bitfield<11> lpae;
623 Bitfield<9> ns;
624 Bitfield<8, 7> sh;
625 Bitfield<0> f;
626 EndBitUnion(PAR)
627
628 BitUnion32(ESR)
629 Bitfield<31, 26> ec;
630 Bitfield<25> il;
631 Bitfield<15, 0> imm16;
632 EndBitUnion(ESR)
633
634 BitUnion32(CPTR)
635 Bitfield<31> tcpac;
636 Bitfield<20> tta;
637 Bitfield<13, 12> res1_13_12_el2;
638 Bitfield<10> tfp;
| 380 Bitfield<19, 18> cp9;
381 Bitfield<21, 20> cp10;
382 Bitfield<21, 20> fpen; // AArch64
383 Bitfield<23, 22> cp11;
384 Bitfield<25, 24> cp12;
385 Bitfield<27, 26> cp13;
386 Bitfield<29, 28> rsvd;
387 Bitfield<28> tta; // AArch64
388 Bitfield<30> d32dis;
389 Bitfield<31> asedis;
390 EndBitUnion(CPACR)
391
392 BitUnion32(FSR)
393 Bitfield<3, 0> fsLow;
394 Bitfield<5, 0> status; // LPAE
395 Bitfield<7, 4> domain;
396 Bitfield<9> lpae;
397 Bitfield<10> fsHigh;
398 Bitfield<11> wnr;
399 Bitfield<12> ext;
400 Bitfield<13> cm; // LPAE
401 EndBitUnion(FSR)
402
403 BitUnion32(FPSCR)
404 Bitfield<0> ioc;
405 Bitfield<1> dzc;
406 Bitfield<2> ofc;
407 Bitfield<3> ufc;
408 Bitfield<4> ixc;
409 Bitfield<7> idc;
410 Bitfield<8> ioe;
411 Bitfield<9> dze;
412 Bitfield<10> ofe;
413 Bitfield<11> ufe;
414 Bitfield<12> ixe;
415 Bitfield<15> ide;
416 Bitfield<18, 16> len;
417 Bitfield<19> fz16;
418 Bitfield<21, 20> stride;
419 Bitfield<23, 22> rMode;
420 Bitfield<24> fz;
421 Bitfield<25> dn;
422 Bitfield<26> ahp;
423 Bitfield<27> qc;
424 Bitfield<28> v;
425 Bitfield<29> c;
426 Bitfield<30> z;
427 Bitfield<31> n;
428 EndBitUnion(FPSCR)
429
430 BitUnion32(FPEXC)
431 Bitfield<31> ex;
432 Bitfield<30> en;
433 Bitfield<29, 0> subArchDefined;
434 EndBitUnion(FPEXC)
435
436 BitUnion32(MVFR0)
437 Bitfield<3, 0> advSimdRegisters;
438 Bitfield<7, 4> singlePrecision;
439 Bitfield<11, 8> doublePrecision;
440 Bitfield<15, 12> vfpExceptionTrapping;
441 Bitfield<19, 16> divide;
442 Bitfield<23, 20> squareRoot;
443 Bitfield<27, 24> shortVectors;
444 Bitfield<31, 28> roundingModes;
445 EndBitUnion(MVFR0)
446
447 BitUnion32(MVFR1)
448 Bitfield<3, 0> flushToZero;
449 Bitfield<7, 4> defaultNaN;
450 Bitfield<11, 8> advSimdLoadStore;
451 Bitfield<15, 12> advSimdInteger;
452 Bitfield<19, 16> advSimdSinglePrecision;
453 Bitfield<23, 20> advSimdHalfPrecision;
454 Bitfield<27, 24> vfpHalfPrecision;
455 Bitfield<31, 28> raz;
456 EndBitUnion(MVFR1)
457
458 BitUnion64(TTBCR)
459 // Short-descriptor translation table format
460 Bitfield<2, 0> n;
461 Bitfield<4> pd0;
462 Bitfield<5> pd1;
463 // Long-descriptor translation table format
464 Bitfield<2, 0> t0sz;
465 Bitfield<6> t2e;
466 Bitfield<7> epd0;
467 Bitfield<9, 8> irgn0;
468 Bitfield<11, 10> orgn0;
469 Bitfield<13, 12> sh0;
470 Bitfield<14> tg0;
471 Bitfield<18, 16> t1sz;
472 Bitfield<22> a1;
473 Bitfield<23> epd1;
474 Bitfield<25, 24> irgn1;
475 Bitfield<27, 26> orgn1;
476 Bitfield<29, 28> sh1;
477 Bitfield<30> tg1;
478 Bitfield<34, 32> ips;
479 Bitfield<36> as;
480 Bitfield<37> tbi0;
481 Bitfield<38> tbi1;
482 // Common
483 Bitfield<31> eae;
484 // TCR_EL2/3 (AArch64)
485 Bitfield<18, 16> ps;
486 Bitfield<20> tbi;
487 Bitfield<41> hpd0;
488 Bitfield<42> hpd1;
489 EndBitUnion(TTBCR)
490
491 // Fields of TCR_EL{1,2,3} (mostly overlapping)
492 // TCR_EL1 is natively 64 bits, the others are 32 bits
493 BitUnion64(TCR)
494 Bitfield<5, 0> t0sz;
495 Bitfield<7> epd0; // EL1
496 Bitfield<9, 8> irgn0;
497 Bitfield<11, 10> orgn0;
498 Bitfield<13, 12> sh0;
499 Bitfield<15, 14> tg0;
500 Bitfield<18, 16> ps;
501 Bitfield<20> tbi; // EL2/EL3
502 Bitfield<21, 16> t1sz; // EL1
503 Bitfield<22> a1; // EL1
504 Bitfield<23> epd1; // EL1
505 Bitfield<25, 24> irgn1; // EL1
506 Bitfield<27, 26> orgn1; // EL1
507 Bitfield<29, 28> sh1; // EL1
508 Bitfield<31, 30> tg1; // EL1
509 Bitfield<34, 32> ips; // EL1
510 Bitfield<36> as; // EL1
511 Bitfield<37> tbi0; // EL1
512 Bitfield<38> tbi1; // EL1
513 Bitfield<39> ha;
514 Bitfield<40> hd;
515 Bitfield<41> hpd0;
516 Bitfield<42> hpd1;
517 EndBitUnion(TCR)
518
519 BitUnion32(HTCR)
520 Bitfield<2, 0> t0sz;
521 Bitfield<9, 8> irgn0;
522 Bitfield<11, 10> orgn0;
523 Bitfield<13, 12> sh0;
524 Bitfield<24> hpd;
525 EndBitUnion(HTCR)
526
527 BitUnion32(VTCR_t)
528 Bitfield<3, 0> t0sz;
529 Bitfield<4> s;
530 Bitfield<5, 0> t0sz64;
531 Bitfield<7, 6> sl0;
532 Bitfield<9, 8> irgn0;
533 Bitfield<11, 10> orgn0;
534 Bitfield<13, 12> sh0;
535 Bitfield<15, 14> tg0;
536 Bitfield<18, 16> ps; // Only defined for VTCR_EL2
537 Bitfield<21> ha; // Only defined for VTCR_EL2
538 Bitfield<22> hd; // Only defined for VTCR_EL2
539 EndBitUnion(VTCR_t)
540
541 BitUnion32(PRRR)
542 Bitfield<1,0> tr0;
543 Bitfield<3,2> tr1;
544 Bitfield<5,4> tr2;
545 Bitfield<7,6> tr3;
546 Bitfield<9,8> tr4;
547 Bitfield<11,10> tr5;
548 Bitfield<13,12> tr6;
549 Bitfield<15,14> tr7;
550 Bitfield<16> ds0;
551 Bitfield<17> ds1;
552 Bitfield<18> ns0;
553 Bitfield<19> ns1;
554 Bitfield<24> nos0;
555 Bitfield<25> nos1;
556 Bitfield<26> nos2;
557 Bitfield<27> nos3;
558 Bitfield<28> nos4;
559 Bitfield<29> nos5;
560 Bitfield<30> nos6;
561 Bitfield<31> nos7;
562 EndBitUnion(PRRR)
563
564 BitUnion32(NMRR)
565 Bitfield<1,0> ir0;
566 Bitfield<3,2> ir1;
567 Bitfield<5,4> ir2;
568 Bitfield<7,6> ir3;
569 Bitfield<9,8> ir4;
570 Bitfield<11,10> ir5;
571 Bitfield<13,12> ir6;
572 Bitfield<15,14> ir7;
573 Bitfield<17,16> or0;
574 Bitfield<19,18> or1;
575 Bitfield<21,20> or2;
576 Bitfield<23,22> or3;
577 Bitfield<25,24> or4;
578 Bitfield<27,26> or5;
579 Bitfield<29,28> or6;
580 Bitfield<31,30> or7;
581 EndBitUnion(NMRR)
582
583 BitUnion32(CONTEXTIDR)
584 Bitfield<7,0> asid;
585 Bitfield<31,8> procid;
586 EndBitUnion(CONTEXTIDR)
587
588 BitUnion32(L2CTLR)
589 Bitfield<2,0> sataRAMLatency;
590 Bitfield<4,3> reserved_4_3;
591 Bitfield<5> dataRAMSetup;
592 Bitfield<8,6> tagRAMLatency;
593 Bitfield<9> tagRAMSetup;
594 Bitfield<11,10> dataRAMSlice;
595 Bitfield<12> tagRAMSlice;
596 Bitfield<20,13> reserved_20_13;
597 Bitfield<21> eccandParityEnable;
598 Bitfield<22> reserved_22;
599 Bitfield<23> interptCtrlPresent;
600 Bitfield<25,24> numCPUs;
601 Bitfield<30,26> reserved_30_26;
602 Bitfield<31> l2rstDISABLE_monitor;
603 EndBitUnion(L2CTLR)
604
605 BitUnion32(CTR)
606 Bitfield<3,0> iCacheLineSize;
607 Bitfield<13,4> raz_13_4;
608 Bitfield<15,14> l1IndexPolicy;
609 Bitfield<19,16> dCacheLineSize;
610 Bitfield<23,20> erg;
611 Bitfield<27,24> cwg;
612 Bitfield<28> raz_28;
613 Bitfield<31,29> format;
614 EndBitUnion(CTR)
615
616 BitUnion32(PMSELR)
617 Bitfield<4, 0> sel;
618 EndBitUnion(PMSELR)
619
620 BitUnion64(PAR)
621 // 64-bit format
622 Bitfield<63, 56> attr;
623 Bitfield<39, 12> pa;
624 Bitfield<11> lpae;
625 Bitfield<9> ns;
626 Bitfield<8, 7> sh;
627 Bitfield<0> f;
628 EndBitUnion(PAR)
629
630 BitUnion32(ESR)
631 Bitfield<31, 26> ec;
632 Bitfield<25> il;
633 Bitfield<15, 0> imm16;
634 EndBitUnion(ESR)
635
636 BitUnion32(CPTR)
637 Bitfield<31> tcpac;
638 Bitfield<20> tta;
639 Bitfield<13, 12> res1_13_12_el2;
640 Bitfield<10> tfp;
|
639 Bitfield<9, 0> res1_9_0_el2;
| 641 Bitfield<9> res1_9_el2;
642 Bitfield<8> res1_8_el2;
643 Bitfield<8> ez; // SVE (CPTR_EL3)
644 Bitfield<8> tz; // SVE (CPTR_EL2)
645 Bitfield<7, 0> res1_7_0_el2;
|
640 EndBitUnion(CPTR)
641
| 646 EndBitUnion(CPTR)
647
|
| 648 BitUnion64(ZCR)
649 Bitfield<3, 0> len;
650 EndBitUnion(ZCR)
651
|
642}
643
644#endif // __ARCH_ARM_MISCREGS_TYPES_HH__
| 652}
653
654#endif // __ARCH_ARM_MISCREGS_TYPES_HH__
|