1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 * Giacomo Gabrielli
42 */
43
44#ifndef __ARCH_ARM_MISCREGS_TYPES_HH__
45#define __ARCH_ARM_MISCREGS_TYPES_HH__
46
47#include "base/bitunion.hh"
48
49namespace ArmISA
50{
51 BitUnion32(CPSR)
52 Bitfield<31, 30> nz;
53 Bitfield<29> c;
54 Bitfield<28> v;
55 Bitfield<27> q;
56 Bitfield<26, 25> it1;
57 Bitfield<24> j;
58 Bitfield<23, 22> res0_23_22;
59 Bitfield<21> ss; // AArch64
60 Bitfield<20> il; // AArch64
61 Bitfield<19, 16> ge;
62 Bitfield<15, 10> it2;
63 Bitfield<9> d; // AArch64
64 Bitfield<9> e;
65 Bitfield<8> a;
66 Bitfield<7> i;
67 Bitfield<6> f;
68 Bitfield<8, 6> aif;
69 Bitfield<9, 6> daif; // AArch64
70 Bitfield<5> t;
71 Bitfield<4> width; // AArch64
72 Bitfield<3, 2> el; // AArch64
73 Bitfield<4, 0> mode;
74 Bitfield<0> sp; // AArch64
75 EndBitUnion(CPSR)
76
77 BitUnion32(HDCR)
78 Bitfield<11> tdra;
79 Bitfield<10> tdosa;
80 Bitfield<9> tda;
81 Bitfield<8> tde;
82 Bitfield<7> hpme;
83 Bitfield<6> tpm;
84 Bitfield<5> tpmcr;
85 Bitfield<4, 0> hpmn;
86 EndBitUnion(HDCR)
87
88 BitUnion32(HCPTR)
89 Bitfield<31> tcpac;
90 Bitfield<20> tta;
91 Bitfield<15> tase;
92 Bitfield<13> tcp13;
93 Bitfield<12> tcp12;
94 Bitfield<11> tcp11;
95 Bitfield<10> tcp10;
96 Bitfield<10> tfp; // AArch64
97 Bitfield<9> tcp9;
98 Bitfield<8> tcp8;
99 Bitfield<7> tcp7;
100 Bitfield<6> tcp6;
101 Bitfield<5> tcp5;
102 Bitfield<4> tcp4;
103 Bitfield<3> tcp3;
104 Bitfield<2> tcp2;
105 Bitfield<1> tcp1;
106 Bitfield<0> tcp0;
107 EndBitUnion(HCPTR)
108
109 BitUnion32(HSTR)
110 Bitfield<17> tjdbx;
111 Bitfield<16> ttee;
112 Bitfield<15> t15;
113 Bitfield<13> t13;
114 Bitfield<12> t12;
115 Bitfield<11> t11;
116 Bitfield<10> t10;
117 Bitfield<9> t9;
118 Bitfield<8> t8;
119 Bitfield<7> t7;
120 Bitfield<6> t6;
121 Bitfield<5> t5;
122 Bitfield<4> t4;
123 Bitfield<3> t3;
124 Bitfield<2> t2;
125 Bitfield<1> t1;
126 Bitfield<0> t0;
127 EndBitUnion(HSTR)
128
129 BitUnion64(HCR)
130 Bitfield<34> e2h; // AArch64
131 Bitfield<33> id; // AArch64
132 Bitfield<32> cd; // AArch64
133 Bitfield<31> rw; // AArch64
134 Bitfield<30> trvm; // AArch64
135 Bitfield<29> hcd; // AArch64
136 Bitfield<28> tdz; // AArch64
137
138 Bitfield<27> tge;
139 Bitfield<26> tvm;
140 Bitfield<25> ttlb;
141 Bitfield<24> tpu;
142 Bitfield<23> tpc;
143 Bitfield<22> tsw;
144 Bitfield<21> tac;
145 Bitfield<21> tacr; // AArch64
146 Bitfield<20> tidcp;
147 Bitfield<19> tsc;
148 Bitfield<18> tid3;
149 Bitfield<17> tid2;
150 Bitfield<16> tid1;
151 Bitfield<15> tid0;
152 Bitfield<14> twe;
153 Bitfield<13> twi;
154 Bitfield<12> dc;
155 Bitfield<11, 10> bsu;
156 Bitfield<9> fb;
157 Bitfield<8> va;
158 Bitfield<8> vse; // AArch64
159 Bitfield<7> vi;
160 Bitfield<6> vf;
161 Bitfield<5> amo;
162 Bitfield<4> imo;
163 Bitfield<3> fmo;
164 Bitfield<2> ptw;
165 Bitfield<1> swio;
166 Bitfield<0> vm;
167 EndBitUnion(HCR)
168
169 BitUnion32(NSACR)
170 Bitfield<20> nstrcdis;
171 Bitfield<19> rfr;
172 Bitfield<15> nsasedis;
173 Bitfield<14> nsd32dis;
174 Bitfield<13> cp13;
175 Bitfield<12> cp12;
176 Bitfield<11> cp11;
177 Bitfield<10> cp10;
178 Bitfield<9> cp9;
179 Bitfield<8> cp8;
180 Bitfield<7> cp7;
181 Bitfield<6> cp6;
182 Bitfield<5> cp5;
183 Bitfield<4> cp4;
184 Bitfield<3> cp3;
185 Bitfield<2> cp2;
186 Bitfield<1> cp1;
187 Bitfield<0> cp0;
188 EndBitUnion(NSACR)
189
190 BitUnion32(SCR)
191 Bitfield<13> twe;
192 Bitfield<12> twi;
193 Bitfield<11> st; // AArch64
194 Bitfield<10> rw; // AArch64
195 Bitfield<9> sif;
196 Bitfield<8> hce;
197 Bitfield<7> scd;
198 Bitfield<7> smd; // AArch64
199 Bitfield<6> nEt;
200 Bitfield<5> aw;
201 Bitfield<4> fw;
202 Bitfield<3> ea;
203 Bitfield<2> fiq;
204 Bitfield<1> irq;
205 Bitfield<0> ns;
206 EndBitUnion(SCR)
207
208 BitUnion32(SCTLR)
209 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
210 Bitfield<29> afe; // Access flag enable (AArch32 only)
211 Bitfield<28> tre; // TEX remap enable (AArch32 only)
212 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
213 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
214 // DC CVAC and IC IVAU instructions
215 // (AArch64 SCTLR_EL1 only)
216 Bitfield<25> ee; // Exception Endianness
217 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
218 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
219 // (AArch64 SCTLR_EL1 only)
220 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
221 Bitfield<22> u; // Alignment (dropped in ARMv7)
222 Bitfield<21> fi; // Fast interrupts configuration enable
223 // (ARMv7 only)
224 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
225 // (AArch32 only)
226 Bitfield<19> dz; // Divide by Zero fault enable
227 // (dropped in ARMv7)
228 Bitfield<19> wxn; // Write permission implies XN
229 Bitfield<18> ntwe; // Not trap WFE
230 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
231 Bitfield<18> rao2; // Read as one
232 Bitfield<16> ntwi; // Not trap WFI
233 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
234 Bitfield<16> rao3; // Read as one
235 Bitfield<15> uct; // Enable EL0 access to CTR_EL0
236 // (AArch64 SCTLR_EL1 only)
237 Bitfield<14> rr; // Round Robin select (ARMv7 only)
238 Bitfield<14> dze; // Enable EL0 access to DC ZVA
239 // (AArch64 SCTLR_EL1 only)
240 Bitfield<13> v; // Vectors bit (AArch32 only)
241 Bitfield<12> i; // Instruction cache enable
242 Bitfield<11> z; // Branch prediction enable (ARMv7 only)
243 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
244 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
245 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
246 Bitfield<8> sed; // SETEND disable
247 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
248 Bitfield<7> b; // Endianness support (dropped in ARMv7)
249 Bitfield<7> itd; // IT disable
250 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
251 Bitfield<6, 3> rao4; // Read as one
252 Bitfield<6> thee; // ThumbEE enable
253 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
254 Bitfield<5> cp15ben; // CP15 barrier enable
255 // (AArch32 and AArch64 SCTLR_EL1 only)
256 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
257 // (AArch64 SCTLR_EL1 only)
258 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
259 Bitfield<2> c; // Cache enable
260 Bitfield<1> a; // Alignment check enable
261 Bitfield<0> m; // MMU enable
262 EndBitUnion(SCTLR)
263
264 BitUnion32(CPACR)
265 Bitfield<1, 0> cp0;
266 Bitfield<3, 2> cp1;
267 Bitfield<5, 4> cp2;
268 Bitfield<7, 6> cp3;
269 Bitfield<9, 8> cp4;
270 Bitfield<11, 10> cp5;
271 Bitfield<13, 12> cp6;
272 Bitfield<15, 14> cp7;
273 Bitfield<17, 16> cp8;
274 Bitfield<19, 18> cp9;
275 Bitfield<21, 20> cp10;
276 Bitfield<21, 20> fpen; // AArch64
277 Bitfield<23, 22> cp11;
278 Bitfield<25, 24> cp12;
279 Bitfield<27, 26> cp13;
280 Bitfield<29, 28> rsvd;
281 Bitfield<28> tta; // AArch64
282 Bitfield<30> d32dis;
283 Bitfield<31> asedis;
284 EndBitUnion(CPACR)
285
286 BitUnion32(FSR)
287 Bitfield<3, 0> fsLow;
288 Bitfield<5, 0> status; // LPAE
289 Bitfield<7, 4> domain;
290 Bitfield<9> lpae;
291 Bitfield<10> fsHigh;
292 Bitfield<11> wnr;
293 Bitfield<12> ext;
294 Bitfield<13> cm; // LPAE
295 EndBitUnion(FSR)
296
297 BitUnion32(FPSCR)
298 Bitfield<0> ioc;
299 Bitfield<1> dzc;
300 Bitfield<2> ofc;
301 Bitfield<3> ufc;
302 Bitfield<4> ixc;
303 Bitfield<7> idc;
304 Bitfield<8> ioe;
305 Bitfield<9> dze;
306 Bitfield<10> ofe;
307 Bitfield<11> ufe;
308 Bitfield<12> ixe;
309 Bitfield<15> ide;
310 Bitfield<18, 16> len;
311 Bitfield<21, 20> stride;
312 Bitfield<23, 22> rMode;
313 Bitfield<24> fz;
314 Bitfield<25> dn;
315 Bitfield<26> ahp;
316 Bitfield<27> qc;
317 Bitfield<28> v;
318 Bitfield<29> c;
319 Bitfield<30> z;
320 Bitfield<31> n;
321 EndBitUnion(FPSCR)
322
323 BitUnion32(FPEXC)
324 Bitfield<31> ex;
325 Bitfield<30> en;
326 Bitfield<29, 0> subArchDefined;
327 EndBitUnion(FPEXC)
328
329 BitUnion32(MVFR0)
330 Bitfield<3, 0> advSimdRegisters;
331 Bitfield<7, 4> singlePrecision;
332 Bitfield<11, 8> doublePrecision;
333 Bitfield<15, 12> vfpExceptionTrapping;
334 Bitfield<19, 16> divide;
335 Bitfield<23, 20> squareRoot;
336 Bitfield<27, 24> shortVectors;
337 Bitfield<31, 28> roundingModes;
338 EndBitUnion(MVFR0)
339
340 BitUnion32(MVFR1)
341 Bitfield<3, 0> flushToZero;
342 Bitfield<7, 4> defaultNaN;
343 Bitfield<11, 8> advSimdLoadStore;
344 Bitfield<15, 12> advSimdInteger;
345 Bitfield<19, 16> advSimdSinglePrecision;
346 Bitfield<23, 20> advSimdHalfPrecision;
347 Bitfield<27, 24> vfpHalfPrecision;
348 Bitfield<31, 28> raz;
349 EndBitUnion(MVFR1)
350
351 BitUnion64(TTBCR)
352 // Short-descriptor translation table format
353 Bitfield<2, 0> n;
354 Bitfield<4> pd0;
355 Bitfield<5> pd1;
356 // Long-descriptor translation table format
357 Bitfield<2, 0> t0sz;
358 Bitfield<7> epd0;
359 Bitfield<9, 8> irgn0;
360 Bitfield<11, 10> orgn0;
361 Bitfield<13, 12> sh0;
362 Bitfield<14> tg0;
363 Bitfield<18, 16> t1sz;
364 Bitfield<22> a1;
365 Bitfield<23> epd1;
366 Bitfield<25, 24> irgn1;
367 Bitfield<27, 26> orgn1;
368 Bitfield<29, 28> sh1;
369 Bitfield<30> tg1;
370 Bitfield<34, 32> ips;
371 Bitfield<36> as;
372 Bitfield<37> tbi0;
373 Bitfield<38> tbi1;
374 // Common
375 Bitfield<31> eae;
376 // TCR_EL2/3 (AArch64)
377 Bitfield<18, 16> ps;
378 Bitfield<20> tbi;
379 EndBitUnion(TTBCR)
380
381 // Fields of TCR_EL{1,2,3} (mostly overlapping)
382 // TCR_EL1 is natively 64 bits, the others are 32 bits
383 BitUnion64(TCR)
384 Bitfield<5, 0> t0sz;
385 Bitfield<7> epd0; // EL1
386 Bitfield<9, 8> irgn0;
387 Bitfield<11, 10> orgn0;
388 Bitfield<13, 12> sh0;
389 Bitfield<15, 14> tg0;
390 Bitfield<18, 16> ps;
391 Bitfield<20> tbi; // EL2/EL3
392 Bitfield<21, 16> t1sz; // EL1
393 Bitfield<22> a1; // EL1
394 Bitfield<23> epd1; // EL1
395 Bitfield<25, 24> irgn1; // EL1
396 Bitfield<27, 26> orgn1; // EL1
397 Bitfield<29, 28> sh1; // EL1
398 Bitfield<31, 30> tg1; // EL1
399 Bitfield<34, 32> ips; // EL1
400 Bitfield<36> as; // EL1
401 Bitfield<37> tbi0; // EL1
402 Bitfield<38> tbi1; // EL1
403 EndBitUnion(TCR)
404
405 BitUnion32(HTCR)
406 Bitfield<2, 0> t0sz;
407 Bitfield<9, 8> irgn0;
408 Bitfield<11, 10> orgn0;
409 Bitfield<13, 12> sh0;
410 EndBitUnion(HTCR)
411
412 BitUnion32(VTCR_t)
413 Bitfield<3, 0> t0sz;
414 Bitfield<4> s;
415 Bitfield<5, 0> t0sz64;
416 Bitfield<7, 6> sl0;
417 Bitfield<9, 8> irgn0;
418 Bitfield<11, 10> orgn0;
419 Bitfield<13, 12> sh0;
420 Bitfield<15, 14> tg0;
421 Bitfield<18, 16> ps; // Only defined for VTCR_EL2
422 EndBitUnion(VTCR_t)
423
424 BitUnion32(PRRR)
425 Bitfield<1,0> tr0;
426 Bitfield<3,2> tr1;
427 Bitfield<5,4> tr2;
428 Bitfield<7,6> tr3;
429 Bitfield<9,8> tr4;
430 Bitfield<11,10> tr5;
431 Bitfield<13,12> tr6;
432 Bitfield<15,14> tr7;
433 Bitfield<16> ds0;
434 Bitfield<17> ds1;
435 Bitfield<18> ns0;
436 Bitfield<19> ns1;
437 Bitfield<24> nos0;
438 Bitfield<25> nos1;
439 Bitfield<26> nos2;
440 Bitfield<27> nos3;
441 Bitfield<28> nos4;
442 Bitfield<29> nos5;
443 Bitfield<30> nos6;
444 Bitfield<31> nos7;
445 EndBitUnion(PRRR)
446
447 BitUnion32(NMRR)
448 Bitfield<1,0> ir0;
449 Bitfield<3,2> ir1;
450 Bitfield<5,4> ir2;
451 Bitfield<7,6> ir3;
452 Bitfield<9,8> ir4;
453 Bitfield<11,10> ir5;
454 Bitfield<13,12> ir6;
455 Bitfield<15,14> ir7;
456 Bitfield<17,16> or0;
457 Bitfield<19,18> or1;
458 Bitfield<21,20> or2;
459 Bitfield<23,22> or3;
460 Bitfield<25,24> or4;
461 Bitfield<27,26> or5;
462 Bitfield<29,28> or6;
463 Bitfield<31,30> or7;
464 EndBitUnion(NMRR)
465
466 BitUnion32(CONTEXTIDR)
467 Bitfield<7,0> asid;
468 Bitfield<31,8> procid;
469 EndBitUnion(CONTEXTIDR)
470
471 BitUnion32(L2CTLR)
472 Bitfield<2,0> sataRAMLatency;
473 Bitfield<4,3> reserved_4_3;
474 Bitfield<5> dataRAMSetup;
475 Bitfield<8,6> tagRAMLatency;
476 Bitfield<9> tagRAMSetup;
477 Bitfield<11,10> dataRAMSlice;
478 Bitfield<12> tagRAMSlice;
479 Bitfield<20,13> reserved_20_13;
480 Bitfield<21> eccandParityEnable;
481 Bitfield<22> reserved_22;
482 Bitfield<23> interptCtrlPresent;
483 Bitfield<25,24> numCPUs;
484 Bitfield<30,26> reserved_30_26;
485 Bitfield<31> l2rstDISABLE_monitor;
486 EndBitUnion(L2CTLR)
487
488 BitUnion32(CTR)
489 Bitfield<3,0> iCacheLineSize;
490 Bitfield<13,4> raz_13_4;
491 Bitfield<15,14> l1IndexPolicy;
492 Bitfield<19,16> dCacheLineSize;
493 Bitfield<23,20> erg;
494 Bitfield<27,24> cwg;
495 Bitfield<28> raz_28;
496 Bitfield<31,29> format;
497 EndBitUnion(CTR)
498
499 BitUnion32(PMSELR)
500 Bitfield<4, 0> sel;
501 EndBitUnion(PMSELR)
502
503 BitUnion64(PAR)
504 // 64-bit format
505 Bitfield<63, 56> attr;
506 Bitfield<39, 12> pa;
507 Bitfield<11> lpae;
508 Bitfield<9> ns;
509 Bitfield<8, 7> sh;
510 Bitfield<0> f;
511 EndBitUnion(PAR)
512
513 BitUnion32(ESR)
514 Bitfield<31, 26> ec;
515 Bitfield<25> il;
516 Bitfield<15, 0> imm16;
517 EndBitUnion(ESR)
518
519 BitUnion32(CPTR)
520 Bitfield<31> tcpac;
521 Bitfield<20> tta;
522 Bitfield<13, 12> res1_13_12_el2;
523 Bitfield<10> tfp;
524 Bitfield<9, 0> res1_9_0_el2;
525 EndBitUnion(CPTR)
526
527}
528
529#endif // __ARCH_ARM_MISCREGS_TYPES_HH__