| miscregs.hh (9959:ad4564da49b5) | miscregs.hh (10037:5cac77888310) |
|---|---|
| 1/* | 1/* |
| 2 * Copyright (c) 2010-2012 ARM Limited | 2 * Copyright (c) 2010-2013 ARM Limited |
| 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 22 unchanged lines hidden (view full) --- 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 22 unchanged lines hidden (view full) --- 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black |
| 41 * Giacomo Gabrielli |
|
| 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 | 42 */ 43#ifndef __ARCH_ARM_MISCREGS_HH__ 44#define __ARCH_ARM_MISCREGS_HH__ 45 |
| 46#include <bitset> 47 |
|
| 45#include "base/bitunion.hh" 46#include "base/compiler.hh" 47 | 48#include "base/bitunion.hh" 49#include "base/compiler.hh" 50 |
| 51class ThreadContext; 52 53 |
|
| 48namespace ArmISA 49{ 50 enum ConditionCode { 51 COND_EQ = 0, 52 COND_NE, // 1 53 COND_CS, // 2 54 COND_CC, // 3 55 COND_MI, // 4 --- 6 unchanged lines hidden (view full) --- 62 COND_LT, // 11 63 COND_GT, // 12 64 COND_LE, // 13 65 COND_AL, // 14 66 COND_UC // 15 67 }; 68 69 enum MiscRegIndex { | 54namespace ArmISA 55{ 56 enum ConditionCode { 57 COND_EQ = 0, 58 COND_NE, // 1 59 COND_CS, // 2 60 COND_CC, // 3 61 COND_MI, // 4 --- 6 unchanged lines hidden (view full) --- 68 COND_LT, // 11 69 COND_GT, // 12 70 COND_LE, // 13 71 COND_AL, // 14 72 COND_UC // 15 73 }; 74 75 enum MiscRegIndex { |
| 70 MISCREG_CPSR = 0, 71 MISCREG_CPSR_Q, 72 MISCREG_SPSR, 73 MISCREG_SPSR_FIQ, 74 MISCREG_SPSR_IRQ, 75 MISCREG_SPSR_SVC, 76 MISCREG_SPSR_MON, 77 MISCREG_SPSR_UND, 78 MISCREG_SPSR_ABT, 79 MISCREG_FPSR, 80 MISCREG_FPSID, 81 MISCREG_FPSCR, 82 MISCREG_FPSCR_QC, // Cumulative saturation flag 83 MISCREG_FPSCR_EXC, // Cumulative FP exception flags 84 MISCREG_FPEXC, 85 MISCREG_MVFR0, 86 MISCREG_MVFR1, 87 MISCREG_SCTLR_RST, 88 MISCREG_SEV_MAILBOX, | 76 MISCREG_CPSR = 0, // 0 77 MISCREG_SPSR, // 1 78 MISCREG_SPSR_FIQ, // 2 79 MISCREG_SPSR_IRQ, // 3 80 MISCREG_SPSR_SVC, // 4 81 MISCREG_SPSR_MON, // 5 82 MISCREG_SPSR_ABT, // 6 83 MISCREG_SPSR_HYP, // 7 84 MISCREG_SPSR_UND, // 8 85 MISCREG_ELR_HYP, // 9 86 MISCREG_FPSID, // 10 87 MISCREG_FPSCR, // 11 88 MISCREG_MVFR1, // 12 89 MISCREG_MVFR0, // 13 90 MISCREG_FPEXC, // 14 |
| 89 | 91 |
| 90 // CP14 registers 91 MISCREG_CP14_START, 92 MISCREG_DBGDIDR = MISCREG_CP14_START, 93 MISCREG_DBGDSCR_INT, 94 MISCREG_DBGDTRRX_INT, 95 MISCREG_DBGTRTX_INT, 96 MISCREG_DBGWFAR, 97 MISCREG_DBGVCR, 98 MISCREG_DBGECR, 99 MISCREG_DBGDSCCR, 100 MISCREG_DBGSMCR, 101 MISCREG_DBGDTRRX_EXT, 102 MISCREG_DBGDSCR_EXT, 103 MISCREG_DBGDTRTX_EXT, 104 MISCREG_DBGDRCR, 105 MISCREG_DBGBVR, 106 MISCREG_DBGBCR, 107 MISCREG_DBGBVR_M, 108 MISCREG_DBGBCR_M, 109 MISCREG_DBGDRAR, 110 MISCREG_DBGBXVR_M, 111 MISCREG_DBGOSLAR, 112 MISCREG_DBGOSSRR, 113 MISCREG_DBGOSDLR, 114 MISCREG_DBGPRCR, 115 MISCREG_DBGPRSR, 116 MISCREG_DBGDSAR, 117 MISCREG_DBGITCTRL, 118 MISCREG_DBGCLAIMSET, 119 MISCREG_DBGCLAIMCLR, 120 MISCREG_DBGAUTHSTATUS, 121 MISCREG_DBGDEVID2, 122 MISCREG_DBGDEVID1, 123 MISCREG_DBGDEVID, 124 MISCREG_TEEHBR, | 92 // Helper registers 93 MISCREG_CPSR_MODE, // 15 94 MISCREG_CPSR_Q, // 16 95 MISCREG_FPSCR_EXC, // 17 96 MISCREG_FPSCR_QC, // 18 97 MISCREG_LOCKADDR, // 19 98 MISCREG_LOCKFLAG, // 20 99 MISCREG_PRRR_MAIR0, // 21 100 MISCREG_PRRR_MAIR0_NS, // 22 101 MISCREG_PRRR_MAIR0_S, // 23 102 MISCREG_NMRR_MAIR1, // 24 103 MISCREG_NMRR_MAIR1_NS, // 25 104 MISCREG_NMRR_MAIR1_S, // 26 105 MISCREG_PMXEVTYPER_PMCCFILTR, // 27 106 MISCREG_SCTLR_RST, // 28 107 MISCREG_SEV_MAILBOX, // 29 |
| 125 | 108 |
| 126 // CP15 registers 127 MISCREG_CP15_START, 128 MISCREG_SCTLR = MISCREG_CP15_START, 129 MISCREG_DCCISW, 130 MISCREG_DCCIMVAC, 131 MISCREG_DCCMVAC, 132 MISCREG_CONTEXTIDR, 133 MISCREG_TPIDRURW, 134 MISCREG_TPIDRURO, 135 MISCREG_TPIDRPRW, 136 MISCREG_CP15ISB, 137 MISCREG_CP15DSB, 138 MISCREG_CP15DMB, 139 MISCREG_CPACR, 140 MISCREG_CLIDR, 141 MISCREG_CCSIDR, 142 MISCREG_CSSELR, 143 MISCREG_ICIALLUIS, 144 MISCREG_ICIALLU, 145 MISCREG_ICIMVAU, 146 MISCREG_BPIMVA, 147 MISCREG_BPIALLIS, 148 MISCREG_BPIALL, 149 MISCREG_MIDR, 150 MISCREG_TTBR0, 151 MISCREG_TTBR1, 152 MISCREG_TLBTR, 153 MISCREG_DACR, 154 MISCREG_TLBIALLIS, 155 MISCREG_TLBIMVAIS, 156 MISCREG_TLBIASIDIS, 157 MISCREG_TLBIMVAAIS, 158 MISCREG_ITLBIALL, 159 MISCREG_ITLBIMVA, 160 MISCREG_ITLBIASID, 161 MISCREG_DTLBIALL, 162 MISCREG_DTLBIMVA, 163 MISCREG_DTLBIASID, 164 MISCREG_TLBIALL, 165 MISCREG_TLBIMVA, 166 MISCREG_TLBIASID, 167 MISCREG_TLBIMVAA, 168 MISCREG_DFSR, 169 MISCREG_IFSR, 170 MISCREG_DFAR, 171 MISCREG_IFAR, 172 MISCREG_MPIDR, 173 MISCREG_PRRR, 174 MISCREG_NMRR, 175 MISCREG_TTBCR, 176 MISCREG_ID_PFR0, 177 MISCREG_CTR, 178 MISCREG_SCR, 179 MISCREG_SDER, 180 MISCREG_PAR, 181 MISCREG_V2PCWPR, 182 MISCREG_V2PCWPW, 183 MISCREG_V2PCWUR, 184 MISCREG_V2PCWUW, 185 MISCREG_V2POWPR, 186 MISCREG_V2POWPW, 187 MISCREG_V2POWUR, 188 MISCREG_V2POWUW, 189 MISCREG_ID_MMFR0, 190 MISCREG_ID_MMFR2, 191 MISCREG_ID_MMFR3, 192 MISCREG_ACTLR, 193 MISCREG_PMCR, 194 MISCREG_PMCCNTR, 195 MISCREG_PMCNTENSET, 196 MISCREG_PMCNTENCLR, 197 MISCREG_PMOVSR, 198 MISCREG_PMSWINC, 199 MISCREG_PMSELR, 200 MISCREG_PMCEID0, 201 MISCREG_PMCEID1, 202 MISCREG_PMC_OTHER, 203 MISCREG_PMXEVCNTR, 204 MISCREG_PMUSERENR, 205 MISCREG_PMINTENSET, 206 MISCREG_PMINTENCLR, 207 MISCREG_ID_ISAR0, 208 MISCREG_ID_ISAR1, 209 MISCREG_ID_ISAR2, 210 MISCREG_ID_ISAR3, 211 MISCREG_ID_ISAR4, 212 MISCREG_ID_ISAR5, 213 MISCREG_LOCKFLAG, 214 MISCREG_LOCKADDR, 215 MISCREG_ID_PFR1, 216 MISCREG_L2CTLR, 217 MISCREG_CP15_UNIMP_START, 218 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 219 MISCREG_ID_DFR0, 220 MISCREG_ID_AFR0, 221 MISCREG_ID_MMFR1, 222 MISCREG_AIDR, 223 MISCREG_ADFSR, 224 MISCREG_AIFSR, 225 MISCREG_DCIMVAC, 226 MISCREG_DCISW, 227 MISCREG_MCCSW, 228 MISCREG_DCCMVAU, 229 MISCREG_NSACR, 230 MISCREG_VBAR, 231 MISCREG_MVBAR, 232 MISCREG_ISR, 233 MISCREG_FCEIDR, 234 MISCREG_L2LATENCY, 235 MISCREG_CRN15, | 109 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) 110 MISCREG_DBGDIDR, // 30 111 MISCREG_DBGDSCRint, // 31 112 MISCREG_DBGDCCINT, // 32 113 MISCREG_DBGDTRTXint, // 33 114 MISCREG_DBGDTRRXint, // 34 115 MISCREG_DBGWFAR, // 35 116 MISCREG_DBGVCR, // 36 117 MISCREG_DBGDTRRXext, // 37 118 MISCREG_DBGDSCRext, // 38 119 MISCREG_DBGDTRTXext, // 39 120 MISCREG_DBGOSECCR, // 40 121 MISCREG_DBGBVR0, // 41 122 MISCREG_DBGBVR1, // 42 123 MISCREG_DBGBVR2, // 43 124 MISCREG_DBGBVR3, // 44 125 MISCREG_DBGBVR4, // 45 126 MISCREG_DBGBVR5, // 46 127 MISCREG_DBGBCR0, // 47 128 MISCREG_DBGBCR1, // 48 129 MISCREG_DBGBCR2, // 49 130 MISCREG_DBGBCR3, // 50 131 MISCREG_DBGBCR4, // 51 132 MISCREG_DBGBCR5, // 52 133 MISCREG_DBGWVR0, // 53 134 MISCREG_DBGWVR1, // 54 135 MISCREG_DBGWVR2, // 55 136 MISCREG_DBGWVR3, // 56 137 MISCREG_DBGWCR0, // 57 138 MISCREG_DBGWCR1, // 58 139 MISCREG_DBGWCR2, // 59 140 MISCREG_DBGWCR3, // 60 141 MISCREG_DBGDRAR, // 61 142 MISCREG_DBGBXVR4, // 62 143 MISCREG_DBGBXVR5, // 63 144 MISCREG_DBGOSLAR, // 64 145 MISCREG_DBGOSLSR, // 65 146 MISCREG_DBGOSDLR, // 66 147 MISCREG_DBGPRCR, // 67 148 MISCREG_DBGDSAR, // 68 149 MISCREG_DBGCLAIMSET, // 69 150 MISCREG_DBGCLAIMCLR, // 70 151 MISCREG_DBGAUTHSTATUS, // 71 152 MISCREG_DBGDEVID2, // 72 153 MISCREG_DBGDEVID1, // 73 154 MISCREG_DBGDEVID0, // 74 155 MISCREG_TEECR, // 75 156 MISCREG_JIDR, // 76 157 MISCREG_TEEHBR, // 77 158 MISCREG_JOSCR, // 78 159 MISCREG_JMCR, // 79 |
| 236 | 160 |
| 161 // AArch32 CP15 registers (system control) 162 MISCREG_MIDR, // 80 163 MISCREG_CTR, // 81 164 MISCREG_TCMTR, // 82 165 MISCREG_TLBTR, // 83 166 MISCREG_MPIDR, // 84 167 MISCREG_REVIDR, // 85 168 MISCREG_ID_PFR0, // 86 169 MISCREG_ID_PFR1, // 87 170 MISCREG_ID_DFR0, // 88 171 MISCREG_ID_AFR0, // 89 172 MISCREG_ID_MMFR0, // 90 173 MISCREG_ID_MMFR1, // 91 174 MISCREG_ID_MMFR2, // 92 175 MISCREG_ID_MMFR3, // 93 176 MISCREG_ID_ISAR0, // 94 177 MISCREG_ID_ISAR1, // 95 178 MISCREG_ID_ISAR2, // 96 179 MISCREG_ID_ISAR3, // 97 180 MISCREG_ID_ISAR4, // 98 181 MISCREG_ID_ISAR5, // 99 182 MISCREG_CCSIDR, // 100 183 MISCREG_CLIDR, // 101 184 MISCREG_AIDR, // 102 185 MISCREG_CSSELR, // 103 186 MISCREG_CSSELR_NS, // 104 187 MISCREG_CSSELR_S, // 105 188 MISCREG_VPIDR, // 106 189 MISCREG_VMPIDR, // 107 190 MISCREG_SCTLR, // 108 191 MISCREG_SCTLR_NS, // 109 192 MISCREG_SCTLR_S, // 110 193 MISCREG_ACTLR, // 111 194 MISCREG_ACTLR_NS, // 112 195 MISCREG_ACTLR_S, // 113 196 MISCREG_CPACR, // 114 197 MISCREG_SCR, // 115 198 MISCREG_SDER, // 116 199 MISCREG_NSACR, // 117 200 MISCREG_HSCTLR, // 118 201 MISCREG_HACTLR, // 119 202 MISCREG_HCR, // 120 203 MISCREG_HDCR, // 121 204 MISCREG_HCPTR, // 122 205 MISCREG_HSTR, // 123 206 MISCREG_HACR, // 124 207 MISCREG_TTBR0, // 125 208 MISCREG_TTBR0_NS, // 126 209 MISCREG_TTBR0_S, // 127 210 MISCREG_TTBR1, // 128 211 MISCREG_TTBR1_NS, // 129 212 MISCREG_TTBR1_S, // 130 213 MISCREG_TTBCR, // 131 214 MISCREG_TTBCR_NS, // 132 215 MISCREG_TTBCR_S, // 133 216 MISCREG_HTCR, // 134 217 MISCREG_VTCR, // 135 218 MISCREG_DACR, // 136 219 MISCREG_DACR_NS, // 137 220 MISCREG_DACR_S, // 138 221 MISCREG_DFSR, // 139 222 MISCREG_DFSR_NS, // 140 223 MISCREG_DFSR_S, // 141 224 MISCREG_IFSR, // 142 225 MISCREG_IFSR_NS, // 143 226 MISCREG_IFSR_S, // 144 227 MISCREG_ADFSR, // 145 228 MISCREG_ADFSR_NS, // 146 229 MISCREG_ADFSR_S, // 147 230 MISCREG_AIFSR, // 148 231 MISCREG_AIFSR_NS, // 149 232 MISCREG_AIFSR_S, // 150 233 MISCREG_HADFSR, // 151 234 MISCREG_HAIFSR, // 152 235 MISCREG_HSR, // 153 236 MISCREG_DFAR, // 154 237 MISCREG_DFAR_NS, // 155 238 MISCREG_DFAR_S, // 156 239 MISCREG_IFAR, // 157 240 MISCREG_IFAR_NS, // 158 241 MISCREG_IFAR_S, // 159 242 MISCREG_HDFAR, // 160 243 MISCREG_HIFAR, // 161 244 MISCREG_HPFAR, // 162 245 MISCREG_ICIALLUIS, // 163 246 MISCREG_BPIALLIS, // 164 247 MISCREG_PAR, // 165 248 MISCREG_PAR_NS, // 166 249 MISCREG_PAR_S, // 167 250 MISCREG_ICIALLU, // 168 251 MISCREG_ICIMVAU, // 169 252 MISCREG_CP15ISB, // 170 253 MISCREG_BPIALL, // 171 254 MISCREG_BPIMVA, // 172 255 MISCREG_DCIMVAC, // 173 256 MISCREG_DCISW, // 174 257 MISCREG_ATS1CPR, // 175 258 MISCREG_ATS1CPW, // 176 259 MISCREG_ATS1CUR, // 177 260 MISCREG_ATS1CUW, // 178 261 MISCREG_ATS12NSOPR, // 179 262 MISCREG_ATS12NSOPW, // 180 263 MISCREG_ATS12NSOUR, // 181 264 MISCREG_ATS12NSOUW, // 182 265 MISCREG_DCCMVAC, // 183 266 MISCREG_DCCSW, // 184 267 MISCREG_CP15DSB, // 185 268 MISCREG_CP15DMB, // 186 269 MISCREG_DCCMVAU, // 187 270 MISCREG_DCCIMVAC, // 188 271 MISCREG_DCCISW, // 189 272 MISCREG_ATS1HR, // 190 273 MISCREG_ATS1HW, // 191 274 MISCREG_TLBIALLIS, // 192 275 MISCREG_TLBIMVAIS, // 193 276 MISCREG_TLBIASIDIS, // 194 277 MISCREG_TLBIMVAAIS, // 195 278 MISCREG_TLBIMVALIS, // 196 279 MISCREG_TLBIMVAALIS, // 197 280 MISCREG_ITLBIALL, // 198 281 MISCREG_ITLBIMVA, // 199 282 MISCREG_ITLBIASID, // 200 283 MISCREG_DTLBIALL, // 201 284 MISCREG_DTLBIMVA, // 202 285 MISCREG_DTLBIASID, // 203 286 MISCREG_TLBIALL, // 204 287 MISCREG_TLBIMVA, // 205 288 MISCREG_TLBIASID, // 206 289 MISCREG_TLBIMVAA, // 207 290 MISCREG_TLBIMVAL, // 208 291 MISCREG_TLBIMVAAL, // 209 292 MISCREG_TLBIIPAS2IS, // 210 293 MISCREG_TLBIIPAS2LIS, // 211 294 MISCREG_TLBIALLHIS, // 212 295 MISCREG_TLBIMVAHIS, // 213 296 MISCREG_TLBIALLNSNHIS, // 214 297 MISCREG_TLBIMVALHIS, // 215 298 MISCREG_TLBIIPAS2, // 216 299 MISCREG_TLBIIPAS2L, // 217 300 MISCREG_TLBIALLH, // 218 301 MISCREG_TLBIMVAH, // 219 302 MISCREG_TLBIALLNSNH, // 220 303 MISCREG_TLBIMVALH, // 221 304 MISCREG_PMCR, // 222 305 MISCREG_PMCNTENSET, // 223 306 MISCREG_PMCNTENCLR, // 224 307 MISCREG_PMOVSR, // 225 308 MISCREG_PMSWINC, // 226 309 MISCREG_PMSELR, // 227 310 MISCREG_PMCEID0, // 228 311 MISCREG_PMCEID1, // 229 312 MISCREG_PMCCNTR, // 230 313 MISCREG_PMXEVTYPER, // 231 314 MISCREG_PMCCFILTR, // 232 315 MISCREG_PMXEVCNTR, // 233 316 MISCREG_PMUSERENR, // 234 317 MISCREG_PMINTENSET, // 235 318 MISCREG_PMINTENCLR, // 236 319 MISCREG_PMOVSSET, // 237 320 MISCREG_L2CTLR, // 238 321 MISCREG_L2ECTLR, // 239 322 MISCREG_PRRR, // 240 323 MISCREG_PRRR_NS, // 241 324 MISCREG_PRRR_S, // 242 325 MISCREG_MAIR0, // 243 326 MISCREG_MAIR0_NS, // 244 327 MISCREG_MAIR0_S, // 245 328 MISCREG_NMRR, // 246 329 MISCREG_NMRR_NS, // 247 330 MISCREG_NMRR_S, // 248 331 MISCREG_MAIR1, // 249 332 MISCREG_MAIR1_NS, // 250 333 MISCREG_MAIR1_S, // 251 334 MISCREG_AMAIR0, // 252 335 MISCREG_AMAIR0_NS, // 253 336 MISCREG_AMAIR0_S, // 254 337 MISCREG_AMAIR1, // 255 338 MISCREG_AMAIR1_NS, // 256 339 MISCREG_AMAIR1_S, // 257 340 MISCREG_HMAIR0, // 258 341 MISCREG_HMAIR1, // 259 342 MISCREG_HAMAIR0, // 260 343 MISCREG_HAMAIR1, // 261 344 MISCREG_VBAR, // 262 345 MISCREG_VBAR_NS, // 263 346 MISCREG_VBAR_S, // 264 347 MISCREG_MVBAR, // 265 348 MISCREG_RMR, // 266 349 MISCREG_ISR, // 267 350 MISCREG_HVBAR, // 268 351 MISCREG_FCSEIDR, // 269 352 MISCREG_CONTEXTIDR, // 270 353 MISCREG_CONTEXTIDR_NS, // 271 354 MISCREG_CONTEXTIDR_S, // 272 355 MISCREG_TPIDRURW, // 273 356 MISCREG_TPIDRURW_NS, // 274 357 MISCREG_TPIDRURW_S, // 275 358 MISCREG_TPIDRURO, // 276 359 MISCREG_TPIDRURO_NS, // 277 360 MISCREG_TPIDRURO_S, // 278 361 MISCREG_TPIDRPRW, // 279 362 MISCREG_TPIDRPRW_NS, // 280 363 MISCREG_TPIDRPRW_S, // 281 364 MISCREG_HTPIDR, // 282 365 MISCREG_CNTFRQ, // 283 366 MISCREG_CNTKCTL, // 284 367 MISCREG_CNTP_TVAL, // 285 368 MISCREG_CNTP_TVAL_NS, // 286 369 MISCREG_CNTP_TVAL_S, // 287 370 MISCREG_CNTP_CTL, // 288 371 MISCREG_CNTP_CTL_NS, // 289 372 MISCREG_CNTP_CTL_S, // 290 373 MISCREG_CNTV_TVAL, // 291 374 MISCREG_CNTV_CTL, // 292 375 MISCREG_CNTHCTL, // 293 376 MISCREG_CNTHP_TVAL, // 294 377 MISCREG_CNTHP_CTL, // 295 378 MISCREG_IL1DATA0, // 296 379 MISCREG_IL1DATA1, // 297 380 MISCREG_IL1DATA2, // 298 381 MISCREG_IL1DATA3, // 299 382 MISCREG_DL1DATA0, // 300 383 MISCREG_DL1DATA1, // 301 384 MISCREG_DL1DATA2, // 302 385 MISCREG_DL1DATA3, // 303 386 MISCREG_DL1DATA4, // 304 387 MISCREG_RAMINDEX, // 305 388 MISCREG_L2ACTLR, // 306 389 MISCREG_CBAR, // 307 390 MISCREG_HTTBR, // 308 391 MISCREG_VTTBR, // 309 392 MISCREG_CNTPCT, // 310 393 MISCREG_CNTVCT, // 311 394 MISCREG_CNTP_CVAL, // 312 395 MISCREG_CNTP_CVAL_NS, // 313 396 MISCREG_CNTP_CVAL_S, // 314 397 MISCREG_CNTV_CVAL, // 315 398 MISCREG_CNTVOFF, // 316 399 MISCREG_CNTHP_CVAL, // 317 400 MISCREG_CPUMERRSR, // 318 401 MISCREG_L2MERRSR, // 319 |
|
| 237 | 402 |
| 238 MISCREG_CP15_END, | 403 // AArch64 registers (Op0=2) 404 MISCREG_MDCCINT_EL1, // 320 405 MISCREG_OSDTRRX_EL1, // 321 406 MISCREG_MDSCR_EL1, // 322 407 MISCREG_OSDTRTX_EL1, // 323 408 MISCREG_OSECCR_EL1, // 324 409 MISCREG_DBGBVR0_EL1, // 325 410 MISCREG_DBGBVR1_EL1, // 326 411 MISCREG_DBGBVR2_EL1, // 327 412 MISCREG_DBGBVR3_EL1, // 328 413 MISCREG_DBGBVR4_EL1, // 329 414 MISCREG_DBGBVR5_EL1, // 330 415 MISCREG_DBGBCR0_EL1, // 331 416 MISCREG_DBGBCR1_EL1, // 332 417 MISCREG_DBGBCR2_EL1, // 333 418 MISCREG_DBGBCR3_EL1, // 334 419 MISCREG_DBGBCR4_EL1, // 335 420 MISCREG_DBGBCR5_EL1, // 336 421 MISCREG_DBGWVR0_EL1, // 337 422 MISCREG_DBGWVR1_EL1, // 338 423 MISCREG_DBGWVR2_EL1, // 339 424 MISCREG_DBGWVR3_EL1, // 340 425 MISCREG_DBGWCR0_EL1, // 341 426 MISCREG_DBGWCR1_EL1, // 342 427 MISCREG_DBGWCR2_EL1, // 343 428 MISCREG_DBGWCR3_EL1, // 344 429 MISCREG_MDCCSR_EL0, // 345 430 MISCREG_MDDTR_EL0, // 346 431 MISCREG_MDDTRTX_EL0, // 347 432 MISCREG_MDDTRRX_EL0, // 348 433 MISCREG_DBGVCR32_EL2, // 349 434 MISCREG_MDRAR_EL1, // 350 435 MISCREG_OSLAR_EL1, // 351 436 MISCREG_OSLSR_EL1, // 352 437 MISCREG_OSDLR_EL1, // 353 438 MISCREG_DBGPRCR_EL1, // 354 439 MISCREG_DBGCLAIMSET_EL1, // 355 440 MISCREG_DBGCLAIMCLR_EL1, // 356 441 MISCREG_DBGAUTHSTATUS_EL1, // 357 442 MISCREG_TEECR32_EL1, // 358 443 MISCREG_TEEHBR32_EL1, // 359 |
| 239 | 444 |
| 240 // Dummy indices 241 MISCREG_NOP = MISCREG_CP15_END, 242 MISCREG_RAZ, | 445 // AArch64 registers (Op0=1,3) 446 MISCREG_MIDR_EL1, // 360 447 MISCREG_MPIDR_EL1, // 361 448 MISCREG_REVIDR_EL1, // 362 449 MISCREG_ID_PFR0_EL1, // 363 450 MISCREG_ID_PFR1_EL1, // 364 451 MISCREG_ID_DFR0_EL1, // 365 452 MISCREG_ID_AFR0_EL1, // 366 453 MISCREG_ID_MMFR0_EL1, // 367 454 MISCREG_ID_MMFR1_EL1, // 368 455 MISCREG_ID_MMFR2_EL1, // 369 456 MISCREG_ID_MMFR3_EL1, // 370 457 MISCREG_ID_ISAR0_EL1, // 371 458 MISCREG_ID_ISAR1_EL1, // 372 459 MISCREG_ID_ISAR2_EL1, // 373 460 MISCREG_ID_ISAR3_EL1, // 374 461 MISCREG_ID_ISAR4_EL1, // 375 462 MISCREG_ID_ISAR5_EL1, // 376 463 MISCREG_MVFR0_EL1, // 377 464 MISCREG_MVFR1_EL1, // 378 465 MISCREG_MVFR2_EL1, // 379 466 MISCREG_ID_AA64PFR0_EL1, // 380 467 MISCREG_ID_AA64PFR1_EL1, // 381 468 MISCREG_ID_AA64DFR0_EL1, // 382 469 MISCREG_ID_AA64DFR1_EL1, // 383 470 MISCREG_ID_AA64AFR0_EL1, // 384 471 MISCREG_ID_AA64AFR1_EL1, // 385 472 MISCREG_ID_AA64ISAR0_EL1, // 386 473 MISCREG_ID_AA64ISAR1_EL1, // 387 474 MISCREG_ID_AA64MMFR0_EL1, // 388 475 MISCREG_ID_AA64MMFR1_EL1, // 389 476 MISCREG_CCSIDR_EL1, // 390 477 MISCREG_CLIDR_EL1, // 391 478 MISCREG_AIDR_EL1, // 392 479 MISCREG_CSSELR_EL1, // 393 480 MISCREG_CTR_EL0, // 394 481 MISCREG_DCZID_EL0, // 395 482 MISCREG_VPIDR_EL2, // 396 483 MISCREG_VMPIDR_EL2, // 397 484 MISCREG_SCTLR_EL1, // 398 485 MISCREG_ACTLR_EL1, // 399 486 MISCREG_CPACR_EL1, // 400 487 MISCREG_SCTLR_EL2, // 401 488 MISCREG_ACTLR_EL2, // 402 489 MISCREG_HCR_EL2, // 403 490 MISCREG_MDCR_EL2, // 404 491 MISCREG_CPTR_EL2, // 405 492 MISCREG_HSTR_EL2, // 406 493 MISCREG_HACR_EL2, // 407 494 MISCREG_SCTLR_EL3, // 408 495 MISCREG_ACTLR_EL3, // 409 496 MISCREG_SCR_EL3, // 410 497 MISCREG_SDER32_EL3, // 411 498 MISCREG_CPTR_EL3, // 412 499 MISCREG_MDCR_EL3, // 413 500 MISCREG_TTBR0_EL1, // 414 501 MISCREG_TTBR1_EL1, // 415 502 MISCREG_TCR_EL1, // 416 503 MISCREG_TTBR0_EL2, // 417 504 MISCREG_TCR_EL2, // 418 505 MISCREG_VTTBR_EL2, // 419 506 MISCREG_VTCR_EL2, // 420 507 MISCREG_TTBR0_EL3, // 421 508 MISCREG_TCR_EL3, // 422 509 MISCREG_DACR32_EL2, // 423 510 MISCREG_SPSR_EL1, // 424 511 MISCREG_ELR_EL1, // 425 512 MISCREG_SP_EL0, // 426 513 MISCREG_SPSEL, // 427 514 MISCREG_CURRENTEL, // 428 515 MISCREG_NZCV, // 429 516 MISCREG_DAIF, // 430 517 MISCREG_FPCR, // 431 518 MISCREG_FPSR, // 432 519 MISCREG_DSPSR_EL0, // 433 520 MISCREG_DLR_EL0, // 434 521 MISCREG_SPSR_EL2, // 435 522 MISCREG_ELR_EL2, // 436 523 MISCREG_SP_EL1, // 437 524 MISCREG_SPSR_IRQ_AA64, // 438 525 MISCREG_SPSR_ABT_AA64, // 439 526 MISCREG_SPSR_UND_AA64, // 440 527 MISCREG_SPSR_FIQ_AA64, // 441 528 MISCREG_SPSR_EL3, // 442 529 MISCREG_ELR_EL3, // 443 530 MISCREG_SP_EL2, // 444 531 MISCREG_AFSR0_EL1, // 445 532 MISCREG_AFSR1_EL1, // 446 533 MISCREG_ESR_EL1, // 447 534 MISCREG_IFSR32_EL2, // 448 535 MISCREG_AFSR0_EL2, // 449 536 MISCREG_AFSR1_EL2, // 450 537 MISCREG_ESR_EL2, // 451 538 MISCREG_FPEXC32_EL2, // 452 539 MISCREG_AFSR0_EL3, // 453 540 MISCREG_AFSR1_EL3, // 454 541 MISCREG_ESR_EL3, // 455 542 MISCREG_FAR_EL1, // 456 543 MISCREG_FAR_EL2, // 457 544 MISCREG_HPFAR_EL2, // 458 545 MISCREG_FAR_EL3, // 459 546 MISCREG_IC_IALLUIS, // 460 547 MISCREG_PAR_EL1, // 461 548 MISCREG_IC_IALLU, // 462 549 MISCREG_DC_IVAC_Xt, // 463 550 MISCREG_DC_ISW_Xt, // 464 551 MISCREG_AT_S1E1R_Xt, // 465 552 MISCREG_AT_S1E1W_Xt, // 466 553 MISCREG_AT_S1E0R_Xt, // 467 554 MISCREG_AT_S1E0W_Xt, // 468 555 MISCREG_DC_CSW_Xt, // 469 556 MISCREG_DC_CISW_Xt, // 470 557 MISCREG_DC_ZVA_Xt, // 471 558 MISCREG_IC_IVAU_Xt, // 472 559 MISCREG_DC_CVAC_Xt, // 473 560 MISCREG_DC_CVAU_Xt, // 474 561 MISCREG_DC_CIVAC_Xt, // 475 562 MISCREG_AT_S1E2R_Xt, // 476 563 MISCREG_AT_S1E2W_Xt, // 477 564 MISCREG_AT_S12E1R_Xt, // 478 565 MISCREG_AT_S12E1W_Xt, // 479 566 MISCREG_AT_S12E0R_Xt, // 480 567 MISCREG_AT_S12E0W_Xt, // 481 568 MISCREG_AT_S1E3R_Xt, // 482 569 MISCREG_AT_S1E3W_Xt, // 483 570 MISCREG_TLBI_VMALLE1IS, // 484 571 MISCREG_TLBI_VAE1IS_Xt, // 485 572 MISCREG_TLBI_ASIDE1IS_Xt, // 486 573 MISCREG_TLBI_VAAE1IS_Xt, // 487 574 MISCREG_TLBI_VALE1IS_Xt, // 488 575 MISCREG_TLBI_VAALE1IS_Xt, // 489 576 MISCREG_TLBI_VMALLE1, // 490 577 MISCREG_TLBI_VAE1_Xt, // 491 578 MISCREG_TLBI_ASIDE1_Xt, // 492 579 MISCREG_TLBI_VAAE1_Xt, // 493 580 MISCREG_TLBI_VALE1_Xt, // 494 581 MISCREG_TLBI_VAALE1_Xt, // 495 582 MISCREG_TLBI_IPAS2E1IS_Xt, // 496 583 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497 584 MISCREG_TLBI_ALLE2IS, // 498 585 MISCREG_TLBI_VAE2IS_Xt, // 499 586 MISCREG_TLBI_ALLE1IS, // 500 587 MISCREG_TLBI_VALE2IS_Xt, // 501 588 MISCREG_TLBI_VMALLS12E1IS, // 502 589 MISCREG_TLBI_IPAS2E1_Xt, // 503 590 MISCREG_TLBI_IPAS2LE1_Xt, // 504 591 MISCREG_TLBI_ALLE2, // 505 592 MISCREG_TLBI_VAE2_Xt, // 506 593 MISCREG_TLBI_ALLE1, // 507 594 MISCREG_TLBI_VALE2_Xt, // 508 595 MISCREG_TLBI_VMALLS12E1, // 509 596 MISCREG_TLBI_ALLE3IS, // 510 597 MISCREG_TLBI_VAE3IS_Xt, // 511 598 MISCREG_TLBI_VALE3IS_Xt, // 512 599 MISCREG_TLBI_ALLE3, // 513 600 MISCREG_TLBI_VAE3_Xt, // 514 601 MISCREG_TLBI_VALE3_Xt, // 515 602 MISCREG_PMINTENSET_EL1, // 516 603 MISCREG_PMINTENCLR_EL1, // 517 604 MISCREG_PMCR_EL0, // 518 605 MISCREG_PMCNTENSET_EL0, // 519 606 MISCREG_PMCNTENCLR_EL0, // 520 607 MISCREG_PMOVSCLR_EL0, // 521 608 MISCREG_PMSWINC_EL0, // 522 609 MISCREG_PMSELR_EL0, // 523 610 MISCREG_PMCEID0_EL0, // 524 611 MISCREG_PMCEID1_EL0, // 525 612 MISCREG_PMCCNTR_EL0, // 526 613 MISCREG_PMXEVTYPER_EL0, // 527 614 MISCREG_PMCCFILTR_EL0, // 528 615 MISCREG_PMXEVCNTR_EL0, // 529 616 MISCREG_PMUSERENR_EL0, // 530 617 MISCREG_PMOVSSET_EL0, // 531 618 MISCREG_MAIR_EL1, // 532 619 MISCREG_AMAIR_EL1, // 533 620 MISCREG_MAIR_EL2, // 534 621 MISCREG_AMAIR_EL2, // 535 622 MISCREG_MAIR_EL3, // 536 623 MISCREG_AMAIR_EL3, // 537 624 MISCREG_L2CTLR_EL1, // 538 625 MISCREG_L2ECTLR_EL1, // 539 626 MISCREG_VBAR_EL1, // 540 627 MISCREG_RVBAR_EL1, // 541 628 MISCREG_ISR_EL1, // 542 629 MISCREG_VBAR_EL2, // 543 630 MISCREG_RVBAR_EL2, // 544 631 MISCREG_VBAR_EL3, // 545 632 MISCREG_RVBAR_EL3, // 546 633 MISCREG_RMR_EL3, // 547 634 MISCREG_CONTEXTIDR_EL1, // 548 635 MISCREG_TPIDR_EL1, // 549 636 MISCREG_TPIDR_EL0, // 550 637 MISCREG_TPIDRRO_EL0, // 551 638 MISCREG_TPIDR_EL2, // 552 639 MISCREG_TPIDR_EL3, // 553 640 MISCREG_CNTKCTL_EL1, // 554 641 MISCREG_CNTFRQ_EL0, // 555 642 MISCREG_CNTPCT_EL0, // 556 643 MISCREG_CNTVCT_EL0, // 557 644 MISCREG_CNTP_TVAL_EL0, // 558 645 MISCREG_CNTP_CTL_EL0, // 559 646 MISCREG_CNTP_CVAL_EL0, // 560 647 MISCREG_CNTV_TVAL_EL0, // 561 648 MISCREG_CNTV_CTL_EL0, // 562 649 MISCREG_CNTV_CVAL_EL0, // 563 650 MISCREG_PMEVCNTR0_EL0, // 564 651 MISCREG_PMEVCNTR1_EL0, // 565 652 MISCREG_PMEVCNTR2_EL0, // 566 653 MISCREG_PMEVCNTR3_EL0, // 567 654 MISCREG_PMEVCNTR4_EL0, // 568 655 MISCREG_PMEVCNTR5_EL0, // 569 656 MISCREG_PMEVTYPER0_EL0, // 570 657 MISCREG_PMEVTYPER1_EL0, // 571 658 MISCREG_PMEVTYPER2_EL0, // 572 659 MISCREG_PMEVTYPER3_EL0, // 573 660 MISCREG_PMEVTYPER4_EL0, // 574 661 MISCREG_PMEVTYPER5_EL0, // 575 662 MISCREG_CNTVOFF_EL2, // 576 663 MISCREG_CNTHCTL_EL2, // 577 664 MISCREG_CNTHP_TVAL_EL2, // 578 665 MISCREG_CNTHP_CTL_EL2, // 579 666 MISCREG_CNTHP_CVAL_EL2, // 580 667 MISCREG_CNTPS_TVAL_EL1, // 581 668 MISCREG_CNTPS_CTL_EL1, // 582 669 MISCREG_CNTPS_CVAL_EL1, // 583 670 MISCREG_IL1DATA0_EL1, // 584 671 MISCREG_IL1DATA1_EL1, // 585 672 MISCREG_IL1DATA2_EL1, // 586 673 MISCREG_IL1DATA3_EL1, // 587 674 MISCREG_DL1DATA0_EL1, // 588 675 MISCREG_DL1DATA1_EL1, // 589 676 MISCREG_DL1DATA2_EL1, // 590 677 MISCREG_DL1DATA3_EL1, // 591 678 MISCREG_DL1DATA4_EL1, // 592 679 MISCREG_L2ACTLR_EL1, // 593 680 MISCREG_CPUACTLR_EL1, // 594 681 MISCREG_CPUECTLR_EL1, // 595 682 MISCREG_CPUMERRSR_EL1, // 596 683 MISCREG_L2MERRSR_EL1, // 597 684 MISCREG_CBAR_EL1, // 598 |
| 243 | 685 |
| 244 NUM_MISCREGS | 686 // Dummy registers 687 MISCREG_NOP, // 599 688 MISCREG_RAZ, // 600 689 MISCREG_CP14_UNIMPL, // 601 690 MISCREG_CP15_UNIMPL, // 602 691 MISCREG_A64_UNIMPL, // 603 692 MISCREG_UNKNOWN, // 604 693 694 NUM_MISCREGS // 605 |
| 245 }; 246 | 695 }; 696 |
| 697 enum MiscRegInfo { 698 MISCREG_IMPLEMENTED, 699 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it 700 // tells whether the instruction should raise a 701 // warning or fail 702 MISCREG_MUTEX, // True if the register corresponds to a pair of 703 // mutually exclusive registers 704 MISCREG_BANKED, // True if the register is banked between the two 705 // security states, and this is the parent node of the 706 // two banked registers 707 MISCREG_BANKED_CHILD, // The entry is one of the child registers that 708 // forms a banked set of regs (along with the 709 // other child regs) 710 711 // Access permissions 712 // User mode 713 MISCREG_USR_NS_RD, 714 MISCREG_USR_NS_WR, 715 MISCREG_USR_S_RD, 716 MISCREG_USR_S_WR, 717 // Privileged modes other than hypervisor or monitor 718 MISCREG_PRI_NS_RD, 719 MISCREG_PRI_NS_WR, 720 MISCREG_PRI_S_RD, 721 MISCREG_PRI_S_WR, 722 // Hypervisor mode 723 MISCREG_HYP_RD, 724 MISCREG_HYP_WR, 725 // Monitor mode, SCR.NS == 0 726 MISCREG_MON_NS0_RD, 727 MISCREG_MON_NS0_WR, 728 // Monitor mode, SCR.NS == 1 729 MISCREG_MON_NS1_RD, 730 MISCREG_MON_NS1_WR, 731 732 NUM_MISCREG_INFOS 733 }; 734 735 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; 736 737 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions |
|
| 247 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 248 unsigned crm, unsigned opc2); | 738 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 739 unsigned crm, unsigned opc2); |
| 740 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, 741 unsigned crn, unsigned crm, 742 unsigned op2); 743 // Whether a particular AArch64 system register is -always- read only. 744 bool aarch64SysRegReadOnly(MiscRegIndex miscReg); |
|
| 249 | 745 |
| 746 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions |
|
| 250 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 251 unsigned crm, unsigned opc2); 252 | 747 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 748 unsigned crm, unsigned opc2); 749 |
| 750 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions 751 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1); |
|
| 253 | 752 |
| 753 |
|
| 254 const char * const miscRegName[] = { | 754 const char * const miscRegName[] = { |
| 255 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 256 "spsr_mon", "spsr_und", "spsr_abt", 257 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 258 "mvfr0", "mvfr1", 259 "sctlr_rst", "sev_mailbox", 260 "DBGDIDR", 261 "DBGDSCR_INT", 262 "DBGDTRRX_INT", 263 "DBGTRTX_INT", 264 "DBGWFAR", 265 "DBGVCR", 266 "DBGECR", 267 "DBGDSCCR", 268 "DBGSMCR", 269 "DBGDTRRX_EXT", 270 "DBGDSCR_EXT", 271 "DBGDTRTX_EXT", 272 "DBGDRCR", 273 "DBGBVR", 274 "DBGBCR", 275 "DBGBVR_M", 276 "DBGBCR_M", 277 "DBGDRAR", 278 "DBGBXVR_M", 279 "DBGOSLAR", 280 "DBGOSSRR", 281 "DBGOSDLR", 282 "DBGPRCR", 283 "DBGPRSR", 284 "DBGDSAR", 285 "DBGITCTRL", 286 "DBGCLAIMSET", 287 "DBGCLAIMCLR", 288 "DBGAUTHSTATUS", 289 "DBGDEVID2", 290 "DBGDEVID1", 291 "DBGDEVID", 292 "TEEHBR", 293 "sctlr", "dccisw", "dccimvac", "dccmvac", 294 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 295 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 296 "clidr", "ccsidr", "csselr", 297 "icialluis", "iciallu", "icimvau", 298 "bpimva", "bpiallis", "bpiall", 299 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 300 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 301 "itlbiall", "itlbimva", "itlbiasid", 302 "dtlbiall", "dtlbimva", "dtlbiasid", 303 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 304 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 305 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 306 "scr", "sder", "par", 307 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 308 "v2powpr", "v2powpw", "v2powur", "v2powuw", 309 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr", 310 "pmcntenset", "pmcntenclr", "pmovsr", 311 "pmswinc", "pmselr", "pmceid0", 312 "pmceid1", "pmc_other", "pmxevcntr", 313 "pmuserenr", "pmintenset", "pmintenclr", 314 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 315 "lockflag", "lockaddr", "id_pfr1", 316 "l2ctlr", 317 // Unimplemented below | 755 "cpsr", 756 "spsr", 757 "spsr_fiq", 758 "spsr_irq", 759 "spsr_svc", 760 "spsr_mon", 761 "spsr_abt", 762 "spsr_hyp", 763 "spsr_und", 764 "elr_hyp", 765 "fpsid", 766 "fpscr", 767 "mvfr1", 768 "mvfr0", 769 "fpexc", 770 771 // Helper registers 772 "cpsr_mode", 773 "cpsr_q", 774 "fpscr_exc", 775 "fpscr_qc", 776 "lockaddr", 777 "lockflag", 778 "prrr_mair0", 779 "prrr_mair0_ns", 780 "prrr_mair0_s", 781 "nmrr_mair1", 782 "nmrr_mair1_ns", 783 "nmrr_mair1_s", 784 "pmxevtyper_pmccfiltr", 785 "sctlr_rst", 786 "sev_mailbox", 787 788 // AArch32 CP14 registers 789 "dbgdidr", 790 "dbgdscrint", 791 "dbgdccint", 792 "dbgdtrtxint", 793 "dbgdtrrxint", 794 "dbgwfar", 795 "dbgvcr", 796 "dbgdtrrxext", 797 "dbgdscrext", 798 "dbgdtrtxext", 799 "dbgoseccr", 800 "dbgbvr0", 801 "dbgbvr1", 802 "dbgbvr2", 803 "dbgbvr3", 804 "dbgbvr4", 805 "dbgbvr5", 806 "dbgbcr0", 807 "dbgbcr1", 808 "dbgbcr2", 809 "dbgbcr3", 810 "dbgbcr4", 811 "dbgbcr5", 812 "dbgwvr0", 813 "dbgwvr1", 814 "dbgwvr2", 815 "dbgwvr3", 816 "dbgwcr0", 817 "dbgwcr1", 818 "dbgwcr2", 819 "dbgwcr3", 820 "dbgdrar", 821 "dbgbxvr4", 822 "dbgbxvr5", 823 "dbgoslar", 824 "dbgoslsr", 825 "dbgosdlr", 826 "dbgprcr", 827 "dbgdsar", 828 "dbgclaimset", 829 "dbgclaimclr", 830 "dbgauthstatus", 831 "dbgdevid2", 832 "dbgdevid1", 833 "dbgdevid0", 834 "teecr", 835 "jidr", 836 "teehbr", 837 "joscr", 838 "jmcr", 839 840 // AArch32 CP15 registers 841 "midr", 842 "ctr", |
| 318 "tcmtr", | 843 "tcmtr", |
| 319 "id_dfr0", "id_afr0", | 844 "tlbtr", 845 "mpidr", 846 "revidr", 847 "id_pfr0", 848 "id_pfr1", 849 "id_dfr0", 850 "id_afr0", 851 "id_mmfr0", |
| 320 "id_mmfr1", | 852 "id_mmfr1", |
| 321 "aidr", "adfsr", "aifsr", 322 "dcimvac", "dcisw", "mccsw", 323 "dccmvau", | 853 "id_mmfr2", 854 "id_mmfr3", 855 "id_isar0", 856 "id_isar1", 857 "id_isar2", 858 "id_isar3", 859 "id_isar4", 860 "id_isar5", 861 "ccsidr", 862 "clidr", 863 "aidr", 864 "csselr", 865 "csselr_ns", 866 "csselr_s", 867 "vpidr", 868 "vmpidr", 869 "sctlr", 870 "sctlr_ns", 871 "sctlr_s", 872 "actlr", 873 "actlr_ns", 874 "actlr_s", 875 "cpacr", 876 "scr", 877 "sder", |
| 324 "nsacr", | 878 "nsacr", |
| 325 "vbar", "mvbar", "isr", "fceidr", "l2latency", 326 "crn15", 327 "nop", "raz" | 879 "hsctlr", 880 "hactlr", 881 "hcr", 882 "hdcr", 883 "hcptr", 884 "hstr", 885 "hacr", 886 "ttbr0", 887 "ttbr0_ns", 888 "ttbr0_s", 889 "ttbr1", 890 "ttbr1_ns", 891 "ttbr1_s", 892 "ttbcr", 893 "ttbcr_ns", 894 "ttbcr_s", 895 "htcr", 896 "vtcr", 897 "dacr", 898 "dacr_ns", 899 "dacr_s", 900 "dfsr", 901 "dfsr_ns", 902 "dfsr_s", 903 "ifsr", 904 "ifsr_ns", 905 "ifsr_s", 906 "adfsr", 907 "adfsr_ns", 908 "adfsr_s", 909 "aifsr", 910 "aifsr_ns", 911 "aifsr_s", 912 "hadfsr", 913 "haifsr", 914 "hsr", 915 "dfar", 916 "dfar_ns", 917 "dfar_s", 918 "ifar", 919 "ifar_ns", 920 "ifar_s", 921 "hdfar", 922 "hifar", 923 "hpfar", 924 "icialluis", 925 "bpiallis", 926 "par", 927 "par_ns", 928 "par_s", 929 "iciallu", 930 "icimvau", 931 "cp15isb", 932 "bpiall", 933 "bpimva", 934 "dcimvac", 935 "dcisw", 936 "ats1cpr", 937 "ats1cpw", 938 "ats1cur", 939 "ats1cuw", 940 "ats12nsopr", 941 "ats12nsopw", 942 "ats12nsour", 943 "ats12nsouw", 944 "dccmvac", 945 "dccsw", 946 "cp15dsb", 947 "cp15dmb", 948 "dccmvau", 949 "dccimvac", 950 "dccisw", 951 "ats1hr", 952 "ats1hw", 953 "tlbiallis", 954 "tlbimvais", 955 "tlbiasidis", 956 "tlbimvaais", 957 "tlbimvalis", 958 "tlbimvaalis", 959 "itlbiall", 960 "itlbimva", 961 "itlbiasid", 962 "dtlbiall", 963 "dtlbimva", 964 "dtlbiasid", 965 "tlbiall", 966 "tlbimva", 967 "tlbiasid", 968 "tlbimvaa", 969 "tlbimval", 970 "tlbimvaal", 971 "tlbiipas2is", 972 "tlbiipas2lis", 973 "tlbiallhis", 974 "tlbimvahis", 975 "tlbiallnsnhis", 976 "tlbimvalhis", 977 "tlbiipas2", 978 "tlbiipas2l", 979 "tlbiallh", 980 "tlbimvah", 981 "tlbiallnsnh", 982 "tlbimvalh", 983 "pmcr", 984 "pmcntenset", 985 "pmcntenclr", 986 "pmovsr", 987 "pmswinc", 988 "pmselr", 989 "pmceid0", 990 "pmceid1", 991 "pmccntr", 992 "pmxevtyper", 993 "pmccfiltr", 994 "pmxevcntr", 995 "pmuserenr", 996 "pmintenset", 997 "pmintenclr", 998 "pmovsset", 999 "l2ctlr", 1000 "l2ectlr", 1001 "prrr", 1002 "prrr_ns", 1003 "prrr_s", 1004 "mair0", 1005 "mair0_ns", 1006 "mair0_s", 1007 "nmrr", 1008 "nmrr_ns", 1009 "nmrr_s", 1010 "mair1", 1011 "mair1_ns", 1012 "mair1_s", 1013 "amair0", 1014 "amair0_ns", 1015 "amair0_s", 1016 "amair1", 1017 "amair1_ns", 1018 "amair1_s", 1019 "hmair0", 1020 "hmair1", 1021 "hamair0", 1022 "hamair1", 1023 "vbar", 1024 "vbar_ns", 1025 "vbar_s", 1026 "mvbar", 1027 "rmr", 1028 "isr", 1029 "hvbar", 1030 "fcseidr", 1031 "contextidr", 1032 "contextidr_ns", 1033 "contextidr_s", 1034 "tpidrurw", 1035 "tpidrurw_ns", 1036 "tpidrurw_s", 1037 "tpidruro", 1038 "tpidruro_ns", 1039 "tpidruro_s", 1040 "tpidrprw", 1041 "tpidrprw_ns", 1042 "tpidrprw_s", 1043 "htpidr", 1044 "cntfrq", 1045 "cntkctl", 1046 "cntp_tval", 1047 "cntp_tval_ns", 1048 "cntp_tval_s", 1049 "cntp_ctl", 1050 "cntp_ctl_ns", 1051 "cntp_ctl_s", 1052 "cntv_tval", 1053 "cntv_ctl", 1054 "cnthctl", 1055 "cnthp_tval", 1056 "cnthp_ctl", 1057 "il1data0", 1058 "il1data1", 1059 "il1data2", 1060 "il1data3", 1061 "dl1data0", 1062 "dl1data1", 1063 "dl1data2", 1064 "dl1data3", 1065 "dl1data4", 1066 "ramindex", 1067 "l2actlr", 1068 "cbar", 1069 "httbr", 1070 "vttbr", 1071 "cntpct", 1072 "cntvct", 1073 "cntp_cval", 1074 "cntp_cval_ns", 1075 "cntp_cval_s", 1076 "cntv_cval", 1077 "cntvoff", 1078 "cnthp_cval", 1079 "cpumerrsr", 1080 "l2merrsr", 1081 1082 // AArch64 registers (Op0=2) 1083 "mdccint_el1", 1084 "osdtrrx_el1", 1085 "mdscr_el1", 1086 "osdtrtx_el1", 1087 "oseccr_el1", 1088 "dbgbvr0_el1", 1089 "dbgbvr1_el1", 1090 "dbgbvr2_el1", 1091 "dbgbvr3_el1", 1092 "dbgbvr4_el1", 1093 "dbgbvr5_el1", 1094 "dbgbcr0_el1", 1095 "dbgbcr1_el1", 1096 "dbgbcr2_el1", 1097 "dbgbcr3_el1", 1098 "dbgbcr4_el1", 1099 "dbgbcr5_el1", 1100 "dbgwvr0_el1", 1101 "dbgwvr1_el1", 1102 "dbgwvr2_el1", 1103 "dbgwvr3_el1", 1104 "dbgwcr0_el1", 1105 "dbgwcr1_el1", 1106 "dbgwcr2_el1", 1107 "dbgwcr3_el1", 1108 "mdccsr_el0", 1109 "mddtr_el0", 1110 "mddtrtx_el0", 1111 "mddtrrx_el0", 1112 "dbgvcr32_el2", 1113 "mdrar_el1", 1114 "oslar_el1", 1115 "oslsr_el1", 1116 "osdlr_el1", 1117 "dbgprcr_el1", 1118 "dbgclaimset_el1", 1119 "dbgclaimclr_el1", 1120 "dbgauthstatus_el1", 1121 "teecr32_el1", 1122 "teehbr32_el1", 1123 1124 // AArch64 registers (Op0=1,3) 1125 "midr_el1", 1126 "mpidr_el1", 1127 "revidr_el1", 1128 "id_pfr0_el1", 1129 "id_pfr1_el1", 1130 "id_dfr0_el1", 1131 "id_afr0_el1", 1132 "id_mmfr0_el1", 1133 "id_mmfr1_el1", 1134 "id_mmfr2_el1", 1135 "id_mmfr3_el1", 1136 "id_isar0_el1", 1137 "id_isar1_el1", 1138 "id_isar2_el1", 1139 "id_isar3_el1", 1140 "id_isar4_el1", 1141 "id_isar5_el1", 1142 "mvfr0_el1", 1143 "mvfr1_el1", 1144 "mvfr2_el1", 1145 "id_aa64pfr0_el1", 1146 "id_aa64pfr1_el1", 1147 "id_aa64dfr0_el1", 1148 "id_aa64dfr1_el1", 1149 "id_aa64afr0_el1", 1150 "id_aa64afr1_el1", 1151 "id_aa64isar0_el1", 1152 "id_aa64isar1_el1", 1153 "id_aa64mmfr0_el1", 1154 "id_aa64mmfr1_el1", 1155 "ccsidr_el1", 1156 "clidr_el1", 1157 "aidr_el1", 1158 "csselr_el1", 1159 "ctr_el0", 1160 "dczid_el0", 1161 "vpidr_el2", 1162 "vmpidr_el2", 1163 "sctlr_el1", 1164 "actlr_el1", 1165 "cpacr_el1", 1166 "sctlr_el2", 1167 "actlr_el2", 1168 "hcr_el2", 1169 "mdcr_el2", 1170 "cptr_el2", 1171 "hstr_el2", 1172 "hacr_el2", 1173 "sctlr_el3", 1174 "actlr_el3", 1175 "scr_el3", 1176 "sder32_el3", 1177 "cptr_el3", 1178 "mdcr_el3", 1179 "ttbr0_el1", 1180 "ttbr1_el1", 1181 "tcr_el1", 1182 "ttbr0_el2", 1183 "tcr_el2", 1184 "vttbr_el2", 1185 "vtcr_el2", 1186 "ttbr0_el3", 1187 "tcr_el3", 1188 "dacr32_el2", 1189 "spsr_el1", 1190 "elr_el1", 1191 "sp_el0", 1192 "spsel", 1193 "currentel", 1194 "nzcv", 1195 "daif", 1196 "fpcr", 1197 "fpsr", 1198 "dspsr_el0", 1199 "dlr_el0", 1200 "spsr_el2", 1201 "elr_el2", 1202 "sp_el1", 1203 "spsr_irq_aa64", 1204 "spsr_abt_aa64", 1205 "spsr_und_aa64", 1206 "spsr_fiq_aa64", 1207 "spsr_el3", 1208 "elr_el3", 1209 "sp_el2", 1210 "afsr0_el1", 1211 "afsr1_el1", 1212 "esr_el1", 1213 "ifsr32_el2", 1214 "afsr0_el2", 1215 "afsr1_el2", 1216 "esr_el2", 1217 "fpexc32_el2", 1218 "afsr0_el3", 1219 "afsr1_el3", 1220 "esr_el3", 1221 "far_el1", 1222 "far_el2", 1223 "hpfar_el2", 1224 "far_el3", 1225 "ic_ialluis", 1226 "par_el1", 1227 "ic_iallu", 1228 "dc_ivac_xt", 1229 "dc_isw_xt", 1230 "at_s1e1r_xt", 1231 "at_s1e1w_xt", 1232 "at_s1e0r_xt", 1233 "at_s1e0w_xt", 1234 "dc_csw_xt", 1235 "dc_cisw_xt", 1236 "dc_zva_xt", 1237 "ic_ivau_xt", 1238 "dc_cvac_xt", 1239 "dc_cvau_xt", 1240 "dc_civac_xt", 1241 "at_s1e2r_xt", 1242 "at_s1e2w_xt", 1243 "at_s12e1r_xt", 1244 "at_s12e1w_xt", 1245 "at_s12e0r_xt", 1246 "at_s12e0w_xt", 1247 "at_s1e3r_xt", 1248 "at_s1e3w_xt", 1249 "tlbi_vmalle1is", 1250 "tlbi_vae1is_xt", 1251 "tlbi_aside1is_xt", 1252 "tlbi_vaae1is_xt", 1253 "tlbi_vale1is_xt", 1254 "tlbi_vaale1is_xt", 1255 "tlbi_vmalle1", 1256 "tlbi_vae1_xt", 1257 "tlbi_aside1_xt", 1258 "tlbi_vaae1_xt", 1259 "tlbi_vale1_xt", 1260 "tlbi_vaale1_xt", 1261 "tlbi_ipas2e1is_xt", 1262 "tlbi_ipas2le1is_xt", 1263 "tlbi_alle2is", 1264 "tlbi_vae2is_xt", 1265 "tlbi_alle1is", 1266 "tlbi_vale2is_xt", 1267 "tlbi_vmalls12e1is", 1268 "tlbi_ipas2e1_xt", 1269 "tlbi_ipas2le1_xt", 1270 "tlbi_alle2", 1271 "tlbi_vae2_xt", 1272 "tlbi_alle1", 1273 "tlbi_vale2_xt", 1274 "tlbi_vmalls12e1", 1275 "tlbi_alle3is", 1276 "tlbi_vae3is_xt", 1277 "tlbi_vale3is_xt", 1278 "tlbi_alle3", 1279 "tlbi_vae3_xt", 1280 "tlbi_vale3_xt", 1281 "pmintenset_el1", 1282 "pmintenclr_el1", 1283 "pmcr_el0", 1284 "pmcntenset_el0", 1285 "pmcntenclr_el0", 1286 "pmovsclr_el0", 1287 "pmswinc_el0", 1288 "pmselr_el0", 1289 "pmceid0_el0", 1290 "pmceid1_el0", 1291 "pmccntr_el0", 1292 "pmxevtyper_el0", 1293 "pmccfiltr_el0", 1294 "pmxevcntr_el0", 1295 "pmuserenr_el0", 1296 "pmovsset_el0", 1297 "mair_el1", 1298 "amair_el1", 1299 "mair_el2", 1300 "amair_el2", 1301 "mair_el3", 1302 "amair_el3", 1303 "l2ctlr_el1", 1304 "l2ectlr_el1", 1305 "vbar_el1", 1306 "rvbar_el1", 1307 "isr_el1", 1308 "vbar_el2", 1309 "rvbar_el2", 1310 "vbar_el3", 1311 "rvbar_el3", 1312 "rmr_el3", 1313 "contextidr_el1", 1314 "tpidr_el1", 1315 "tpidr_el0", 1316 "tpidrro_el0", 1317 "tpidr_el2", 1318 "tpidr_el3", 1319 "cntkctl_el1", 1320 "cntfrq_el0", 1321 "cntpct_el0", 1322 "cntvct_el0", 1323 "cntp_tval_el0", 1324 "cntp_ctl_el0", 1325 "cntp_cval_el0", 1326 "cntv_tval_el0", 1327 "cntv_ctl_el0", 1328 "cntv_cval_el0", 1329 "pmevcntr0_el0", 1330 "pmevcntr1_el0", 1331 "pmevcntr2_el0", 1332 "pmevcntr3_el0", 1333 "pmevcntr4_el0", 1334 "pmevcntr5_el0", 1335 "pmevtyper0_el0", 1336 "pmevtyper1_el0", 1337 "pmevtyper2_el0", 1338 "pmevtyper3_el0", 1339 "pmevtyper4_el0", 1340 "pmevtyper5_el0", 1341 "cntvoff_el2", 1342 "cnthctl_el2", 1343 "cnthp_tval_el2", 1344 "cnthp_ctl_el2", 1345 "cnthp_cval_el2", 1346 "cntps_tval_el1", 1347 "cntps_ctl_el1", 1348 "cntps_cval_el1", 1349 "il1data0_el1", 1350 "il1data1_el1", 1351 "il1data2_el1", 1352 "il1data3_el1", 1353 "dl1data0_el1", 1354 "dl1data1_el1", 1355 "dl1data2_el1", 1356 "dl1data3_el1", 1357 "dl1data4_el1", 1358 "l2actlr_el1", 1359 "cpuactlr_el1", 1360 "cpuectlr_el1", 1361 "cpumerrsr_el1", 1362 "l2merrsr_el1", 1363 "cbar_el1", 1364 1365 // Dummy registers 1366 "nop", 1367 "raz", 1368 "cp14_unimpl", 1369 "cp15_unimpl", 1370 "a64_unimpl", 1371 "unknown" |
| 328 }; 329 330 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 331 "The miscRegName array and NUM_MISCREGS are inconsistent."); 332 333 BitUnion32(CPSR) | 1372 }; 1373 1374 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 1375 "The miscRegName array and NUM_MISCREGS are inconsistent."); 1376 1377 BitUnion32(CPSR) |
| 334 Bitfield<31,30> nz; | 1378 Bitfield<31, 30> nz; |
| 335 Bitfield<29> c; 336 Bitfield<28> v; 337 Bitfield<27> q; | 1379 Bitfield<29> c; 1380 Bitfield<28> v; 1381 Bitfield<27> q; |
| 338 Bitfield<26,25> it1; | 1382 Bitfield<26, 25> it1; |
| 339 Bitfield<24> j; | 1383 Bitfield<24> j; |
| 1384 Bitfield<23, 22> res0_23_22; 1385 Bitfield<21> ss; // AArch64 1386 Bitfield<20> il; // AArch64 |
|
| 340 Bitfield<19, 16> ge; | 1387 Bitfield<19, 16> ge; |
| 341 Bitfield<15,10> it2; | 1388 Bitfield<15, 10> it2; 1389 Bitfield<9> d; // AArch64 |
| 342 Bitfield<9> e; 343 Bitfield<8> a; 344 Bitfield<7> i; 345 Bitfield<6> f; | 1390 Bitfield<9> e; 1391 Bitfield<8> a; 1392 Bitfield<7> i; 1393 Bitfield<6> f; |
| 1394 Bitfield<9, 6> daif; // AArch64 |
|
| 346 Bitfield<5> t; | 1395 Bitfield<5> t; |
| 1396 Bitfield<4> width; // AArch64 1397 Bitfield<3, 2> el; // AArch64 |
|
| 347 Bitfield<4, 0> mode; | 1398 Bitfield<4, 0> mode; |
| 1399 Bitfield<0> sp; // AArch64 |
|
| 348 EndBitUnion(CPSR) 349 350 // This mask selects bits of the CPSR that actually go in the CondCodes 351 // integer register to allow renaming. 352 static const uint32_t CondCodesMask = 0xF00F0000; 353 static const uint32_t CpsrMaskQ = 0x08000000; 354 | 1400 EndBitUnion(CPSR) 1401 1402 // This mask selects bits of the CPSR that actually go in the CondCodes 1403 // integer register to allow renaming. 1404 static const uint32_t CondCodesMask = 0xF00F0000; 1405 static const uint32_t CpsrMaskQ = 0x08000000; 1406 |
| 1407 BitUnion32(HDCR) 1408 Bitfield<11> tdra; 1409 Bitfield<10> tdosa; 1410 Bitfield<9> tda; 1411 Bitfield<8> tde; 1412 Bitfield<7> hpme; 1413 Bitfield<6> tpm; 1414 Bitfield<5> tpmcr; 1415 Bitfield<4, 0> hpmn; 1416 EndBitUnion(HDCR) 1417 1418 BitUnion32(HCPTR) 1419 Bitfield<31> tcpac; 1420 Bitfield<20> tta; 1421 Bitfield<15> tase; 1422 Bitfield<13> tcp13; 1423 Bitfield<12> tcp12; 1424 Bitfield<11> tcp11; 1425 Bitfield<10> tcp10; 1426 Bitfield<10> tfp; // AArch64 1427 Bitfield<9> tcp9; 1428 Bitfield<8> tcp8; 1429 Bitfield<7> tcp7; 1430 Bitfield<6> tcp6; 1431 Bitfield<5> tcp5; 1432 Bitfield<4> tcp4; 1433 Bitfield<3> tcp3; 1434 Bitfield<2> tcp2; 1435 Bitfield<1> tcp1; 1436 Bitfield<0> tcp0; 1437 EndBitUnion(HCPTR) 1438 1439 BitUnion32(HSTR) 1440 Bitfield<17> tjdbx; 1441 Bitfield<16> ttee; 1442 Bitfield<15> t15; 1443 Bitfield<13> t13; 1444 Bitfield<12> t12; 1445 Bitfield<11> t11; 1446 Bitfield<10> t10; 1447 Bitfield<9> t9; 1448 Bitfield<8> t8; 1449 Bitfield<7> t7; 1450 Bitfield<6> t6; 1451 Bitfield<5> t5; 1452 Bitfield<4> t4; 1453 Bitfield<3> t3; 1454 Bitfield<2> t2; 1455 Bitfield<1> t1; 1456 Bitfield<0> t0; 1457 EndBitUnion(HSTR) 1458 1459 BitUnion64(HCR) 1460 Bitfield<33> id; // AArch64 1461 Bitfield<32> cd; // AArch64 1462 Bitfield<31> rw; // AArch64 1463 Bitfield<30> trvm; // AArch64 1464 Bitfield<29> hcd; // AArch64 1465 Bitfield<28> tdz; // AArch64 1466 1467 Bitfield<27> tge; 1468 Bitfield<26> tvm; 1469 Bitfield<25> ttlb; 1470 Bitfield<24> tpu; 1471 Bitfield<23> tpc; 1472 Bitfield<22> tsw; 1473 Bitfield<21> tac; 1474 Bitfield<21> tacr; // AArch64 1475 Bitfield<20> tidcp; 1476 Bitfield<19> tsc; 1477 Bitfield<18> tid3; 1478 Bitfield<17> tid2; 1479 Bitfield<16> tid1; 1480 Bitfield<15> tid0; 1481 Bitfield<14> twe; 1482 Bitfield<13> twi; 1483 Bitfield<12> dc; 1484 Bitfield<11, 10> bsu; 1485 Bitfield<9> fb; 1486 Bitfield<8> va; 1487 Bitfield<8> vse; // AArch64 1488 Bitfield<7> vi; 1489 Bitfield<6> vf; 1490 Bitfield<5> amo; 1491 Bitfield<4> imo; 1492 Bitfield<3> fmo; 1493 Bitfield<2> ptw; 1494 Bitfield<1> swio; 1495 Bitfield<0> vm; 1496 EndBitUnion(HCR) 1497 1498 BitUnion32(NSACR) 1499 Bitfield<20> nstrcdis; 1500 Bitfield<19> rfr; 1501 Bitfield<15> nsasedis; 1502 Bitfield<14> nsd32dis; 1503 Bitfield<13> cp13; 1504 Bitfield<12> cp12; 1505 Bitfield<11> cp11; 1506 Bitfield<10> cp10; 1507 Bitfield<9> cp9; 1508 Bitfield<8> cp8; 1509 Bitfield<7> cp7; 1510 Bitfield<6> cp6; 1511 Bitfield<5> cp5; 1512 Bitfield<4> cp4; 1513 Bitfield<3> cp3; 1514 Bitfield<2> cp2; 1515 Bitfield<1> cp1; 1516 Bitfield<0> cp0; 1517 EndBitUnion(NSACR) 1518 1519 BitUnion32(SCR) 1520 Bitfield<13> twe; 1521 Bitfield<12> twi; 1522 Bitfield<11> st; // AArch64 1523 Bitfield<10> rw; // AArch64 1524 Bitfield<9> sif; 1525 Bitfield<8> hce; 1526 Bitfield<7> scd; 1527 Bitfield<7> smd; // AArch64 1528 Bitfield<6> nEt; 1529 Bitfield<5> aw; 1530 Bitfield<4> fw; 1531 Bitfield<3> ea; 1532 Bitfield<2> fiq; 1533 Bitfield<1> irq; 1534 Bitfield<0> ns; 1535 EndBitUnion(SCR) 1536 |
|
| 355 BitUnion32(SCTLR) | 1537 BitUnion32(SCTLR) |
| 356 Bitfield<31> ie; // Instruction endianness 357 Bitfield<30> te; // Thumb Exception Enable 358 Bitfield<29> afe; // Access flag enable 359 Bitfield<28> tre; // TEX Remap bit 360 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 361 Bitfield<25> ee; // Exception Endianness bit 362 Bitfield<24> ve; // Interrupt vectors enable 363 Bitfield<23> xp; // Extended page table enable bit 364 Bitfield<22> u; // Alignment (now unused) 365 Bitfield<21> fi; // Fast interrupts configuration enable 366 Bitfield<19> dz; // Divide by Zero fault enable bit 367 Bitfield<18> rao2;// Read as one 368 Bitfield<17> br; // Background region bit 369 Bitfield<16> rao3;// Read as one 370 Bitfield<14> rr; // Round robin cache replacement 371 Bitfield<13> v; // Base address for exception vectors 372 Bitfield<12> i; // instruction cache enable 373 Bitfield<11> z; // branch prediction enable bit 374 Bitfield<10> sw; // Enable swp/swpb 375 Bitfield<9,8> rs; // deprecated protection bits 376 Bitfield<6,3> rao4;// Read as one 377 Bitfield<7> b; // Endianness support (unused) 378 Bitfield<2> c; // Cache enable bit 379 Bitfield<1> a; // Alignment fault checking 380 Bitfield<0> m; // MMU enable bit | 1538 Bitfield<30> te; // Thumb Exception Enable (AArch32 only) 1539 Bitfield<29> afe; // Access flag enable (AArch32 only) 1540 Bitfield<28> tre; // TEX remap enable (AArch32 only) 1541 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only) 1542 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC, 1543 // DC CVAC and IC IVAU instructions 1544 // (AArch64 SCTLR_EL1 only) 1545 Bitfield<25> ee; // Exception Endianness 1546 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only) 1547 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0 1548 // (AArch64 SCTLR_EL1 only) 1549 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7) 1550 Bitfield<22> u; // Alignment (dropped in ARMv7) 1551 Bitfield<21> fi; // Fast interrupts configuration enable 1552 // (ARMv7 only) 1553 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN 1554 // (AArch32 only) 1555 Bitfield<19> dz; // Divide by Zero fault enable 1556 // (dropped in ARMv7) 1557 Bitfield<19> wxn; // Write permission implies XN 1558 Bitfield<18> ntwe; // Not trap WFE 1559 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1560 Bitfield<18> rao2; // Read as one 1561 Bitfield<16> ntwi; // Not trap WFI 1562 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1563 Bitfield<16> rao3; // Read as one 1564 Bitfield<15> uct; // Enable EL0 access to CTR_EL0 1565 // (AArch64 SCTLR_EL1 only) 1566 Bitfield<14> rr; // Round Robin select (ARMv7 only) 1567 Bitfield<14> dze; // Enable EL0 access to DC ZVA 1568 // (AArch64 SCTLR_EL1 only) 1569 Bitfield<13> v; // Vectors bit (AArch32 only) 1570 Bitfield<12> i; // Instruction cache enable 1571 Bitfield<11> z; // Branch prediction enable (ARMv7 only) 1572 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only) 1573 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7) 1574 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only) 1575 Bitfield<8> sed; // SETEND disable 1576 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1577 Bitfield<7> b; // Endianness support (dropped in ARMv7) 1578 Bitfield<7> itd; // IT disable 1579 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1580 Bitfield<6, 3> rao4; // Read as one 1581 Bitfield<6> thee; // ThumbEE enable 1582 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 1583 Bitfield<5> cp15ben; // CP15 barrier enable 1584 // (AArch32 and AArch64 SCTLR_EL1 only) 1585 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0 1586 // (AArch64 SCTLR_EL1 only) 1587 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only) 1588 Bitfield<2> c; // Cache enable 1589 Bitfield<1> a; // Alignment check enable 1590 Bitfield<0> m; // MMU enable |
| 381 EndBitUnion(SCTLR) 382 383 BitUnion32(CPACR) 384 Bitfield<1, 0> cp0; 385 Bitfield<3, 2> cp1; 386 Bitfield<5, 4> cp2; 387 Bitfield<7, 6> cp3; 388 Bitfield<9, 8> cp4; 389 Bitfield<11, 10> cp5; 390 Bitfield<13, 12> cp6; 391 Bitfield<15, 14> cp7; 392 Bitfield<17, 16> cp8; 393 Bitfield<19, 18> cp9; 394 Bitfield<21, 20> cp10; | 1591 EndBitUnion(SCTLR) 1592 1593 BitUnion32(CPACR) 1594 Bitfield<1, 0> cp0; 1595 Bitfield<3, 2> cp1; 1596 Bitfield<5, 4> cp2; 1597 Bitfield<7, 6> cp3; 1598 Bitfield<9, 8> cp4; 1599 Bitfield<11, 10> cp5; 1600 Bitfield<13, 12> cp6; 1601 Bitfield<15, 14> cp7; 1602 Bitfield<17, 16> cp8; 1603 Bitfield<19, 18> cp9; 1604 Bitfield<21, 20> cp10; |
| 1605 Bitfield<21, 20> fpen; // AArch64 |
|
| 395 Bitfield<23, 22> cp11; 396 Bitfield<25, 24> cp12; 397 Bitfield<27, 26> cp13; 398 Bitfield<29, 28> rsvd; | 1606 Bitfield<23, 22> cp11; 1607 Bitfield<25, 24> cp12; 1608 Bitfield<27, 26> cp13; 1609 Bitfield<29, 28> rsvd; |
| 1610 Bitfield<28> tta; // AArch64 |
|
| 399 Bitfield<30> d32dis; 400 Bitfield<31> asedis; 401 EndBitUnion(CPACR) 402 403 BitUnion32(FSR) 404 Bitfield<3, 0> fsLow; | 1611 Bitfield<30> d32dis; 1612 Bitfield<31> asedis; 1613 EndBitUnion(CPACR) 1614 1615 BitUnion32(FSR) 1616 Bitfield<3, 0> fsLow; |
| 1617 Bitfield<5, 0> status; // LPAE |
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| 405 Bitfield<7, 4> domain; | 1618 Bitfield<7, 4> domain; |
| 1619 Bitfield<9> lpae; |
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| 406 Bitfield<10> fsHigh; 407 Bitfield<11> wnr; 408 Bitfield<12> ext; | 1620 Bitfield<10> fsHigh; 1621 Bitfield<11> wnr; 1622 Bitfield<12> ext; |
| 1623 Bitfield<13> cm; // LPAE |
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| 409 EndBitUnion(FSR) 410 411 BitUnion32(FPSCR) 412 Bitfield<0> ioc; 413 Bitfield<1> dzc; 414 Bitfield<2> ofc; 415 Bitfield<3> ufc; 416 Bitfield<4> ixc; --- 48 unchanged lines hidden (view full) --- 465 Bitfield<11, 8> advSimdLoadStore; 466 Bitfield<15, 12> advSimdInteger; 467 Bitfield<19, 16> advSimdSinglePrecision; 468 Bitfield<23, 20> advSimdHalfPrecision; 469 Bitfield<27, 24> vfpHalfPrecision; 470 Bitfield<31, 28> raz; 471 EndBitUnion(MVFR1) 472 | 1624 EndBitUnion(FSR) 1625 1626 BitUnion32(FPSCR) 1627 Bitfield<0> ioc; 1628 Bitfield<1> dzc; 1629 Bitfield<2> ofc; 1630 Bitfield<3> ufc; 1631 Bitfield<4> ixc; --- 48 unchanged lines hidden (view full) --- 1680 Bitfield<11, 8> advSimdLoadStore; 1681 Bitfield<15, 12> advSimdInteger; 1682 Bitfield<19, 16> advSimdSinglePrecision; 1683 Bitfield<23, 20> advSimdHalfPrecision; 1684 Bitfield<27, 24> vfpHalfPrecision; 1685 Bitfield<31, 28> raz; 1686 EndBitUnion(MVFR1) 1687 |
| 1688 BitUnion64(TTBCR) 1689 // Short-descriptor translation table format 1690 Bitfield<2, 0> n; 1691 Bitfield<4> pd0; 1692 Bitfield<5> pd1; 1693 // Long-descriptor translation table format 1694 Bitfield<5, 0> t0sz; 1695 Bitfield<7> epd0; 1696 Bitfield<9, 8> irgn0; 1697 Bitfield<11, 10> orgn0; 1698 Bitfield<13, 12> sh0; 1699 Bitfield<14> tg0; 1700 Bitfield<21, 16> t1sz; 1701 Bitfield<22> a1; 1702 Bitfield<23> epd1; 1703 Bitfield<25, 24> irgn1; 1704 Bitfield<27, 26> orgn1; 1705 Bitfield<29, 28> sh1; 1706 Bitfield<30> tg1; 1707 Bitfield<34, 32> ips; 1708 Bitfield<36> as; 1709 Bitfield<37> tbi0; 1710 Bitfield<38> tbi1; 1711 // Common 1712 Bitfield<31> eae; 1713 // TCR_EL2/3 (AArch64) 1714 Bitfield<18, 16> ps; 1715 Bitfield<20> tbi; 1716 EndBitUnion(TTBCR) 1717 1718 BitUnion32(HTCR) 1719 Bitfield<2, 0> t0sz; 1720 Bitfield<9, 8> irgn0; 1721 Bitfield<11, 10> orgn0; 1722 Bitfield<13, 12> sh0; 1723 EndBitUnion(HTCR) 1724 1725 BitUnion32(VTCR_t) 1726 Bitfield<3, 0> t0sz; 1727 Bitfield<4> s; 1728 Bitfield<7, 6> sl0; 1729 Bitfield<9, 8> irgn0; 1730 Bitfield<11, 10> orgn0; 1731 Bitfield<13, 12> sh0; 1732 EndBitUnion(VTCR_t) 1733 |
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| 473 BitUnion32(PRRR) 474 Bitfield<1,0> tr0; 475 Bitfield<3,2> tr1; 476 Bitfield<5,4> tr2; 477 Bitfield<7,6> tr3; 478 Bitfield<9,8> tr4; 479 Bitfield<11,10> tr5; 480 Bitfield<13,12> tr6; --- 58 unchanged lines hidden (view full) --- 539 Bitfield<13,4> raz_13_4; 540 Bitfield<15,14> l1IndexPolicy; 541 Bitfield<19,16> dCacheLineSize; 542 Bitfield<23,20> erg; 543 Bitfield<27,24> cwg; 544 Bitfield<28> raz_28; 545 Bitfield<31,29> format; 546 EndBitUnion(CTR) | 1734 BitUnion32(PRRR) 1735 Bitfield<1,0> tr0; 1736 Bitfield<3,2> tr1; 1737 Bitfield<5,4> tr2; 1738 Bitfield<7,6> tr3; 1739 Bitfield<9,8> tr4; 1740 Bitfield<11,10> tr5; 1741 Bitfield<13,12> tr6; --- 58 unchanged lines hidden (view full) --- 1800 Bitfield<13,4> raz_13_4; 1801 Bitfield<15,14> l1IndexPolicy; 1802 Bitfield<19,16> dCacheLineSize; 1803 Bitfield<23,20> erg; 1804 Bitfield<27,24> cwg; 1805 Bitfield<28> raz_28; 1806 Bitfield<31,29> format; 1807 EndBitUnion(CTR) |
| 1808 1809 BitUnion32(PMSELR) 1810 Bitfield<4, 0> sel; 1811 EndBitUnion(PMSELR) 1812 1813 BitUnion64(PAR) 1814 // 64-bit format 1815 Bitfield<63, 56> attr; 1816 Bitfield<39, 12> pa; 1817 Bitfield<11> lpae; 1818 Bitfield<9> ns; 1819 Bitfield<8, 7> sh; 1820 Bitfield<0> f; 1821 EndBitUnion(PAR) 1822 1823 BitUnion32(ESR) 1824 Bitfield<31, 26> ec; 1825 Bitfield<25> il; 1826 Bitfield<15, 0> imm16; 1827 EndBitUnion(ESR) 1828 1829 BitUnion32(CPTR) 1830 Bitfield<31> tcpac; 1831 Bitfield<20> tta; 1832 Bitfield<13, 12> res1_13_12_el2; 1833 Bitfield<10> tfp; 1834 Bitfield<9, 0> res1_9_0_el2; 1835 EndBitUnion(CPTR) 1836 1837 1838 // Checks read access permissions to coproc. registers 1839 bool canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1840 ThreadContext *tc); 1841 1842 // Checks write access permissions to coproc. registers 1843 bool canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1844 ThreadContext *tc); 1845 1846 // Checks read access permissions to AArch64 system registers 1847 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1848 ThreadContext *tc); 1849 1850 // Checks write access permissions to AArch64 system registers 1851 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1852 ThreadContext *tc); 1853 1854 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful 1855 // for MCR/MRC instructions 1856 int 1857 flattenMiscRegNsBanked(int reg, ThreadContext *tc); 1858 1859 // Flattens a misc reg index using the specified security state. This is 1860 // used for opperations (eg address translations) where the security 1861 // state of the register access may differ from the current state of the 1862 // processor 1863 int 1864 flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns); 1865 1866 // Takes a misc reg index and returns the root reg if its one of a set of 1867 // banked registers 1868 void 1869 preUnflattenMiscReg(); 1870 1871 int 1872 unflattenMiscReg(int reg); 1873 |
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| 547} 548 549#endif // __ARCH_ARM_MISCREGS_HH__ | 1874} 1875 1876#endif // __ARCH_ARM_MISCREGS_HH__ |