miscregs.hh (9130:8423aa8c2216) miscregs.hh (9256:f14188a5a1d6)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46#include "base/compiler.hh"
46
47namespace ArmISA
48{
49 enum ConditionCode {
50 COND_EQ = 0,
51 COND_NE, // 1
52 COND_CS, // 2
53 COND_CC, // 3

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245
246 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
247 unsigned crm, unsigned opc2);
248
249 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
250 unsigned crm, unsigned opc2);
251
252
47
48namespace ArmISA
49{
50 enum ConditionCode {
51 COND_EQ = 0,
52 COND_NE, // 1
53 COND_CS, // 2
54 COND_CC, // 3

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246
247 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
248 unsigned crm, unsigned opc2);
249
250 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
251 unsigned crm, unsigned opc2);
252
253
253 const char * const miscRegName[NUM_MISCREGS] = {
254 const char * const miscRegName[] = {
254 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
255 "spsr_mon", "spsr_und", "spsr_abt",
256 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
257 "mvfr0", "mvfr1",
258 "sctlr_rst", "sev_mailbox",
259 "DBGDIDR",
260 "DBGDSCR_INT",
261 "DBGDTRRX_INT",

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320 "dcimvac", "dcisw", "mccsw",
321 "dccmvau",
322 "nsacr",
323 "vbar", "mvbar", "isr", "fceidr", "l2latency",
324 "crn15",
325 "nop", "raz"
326 };
327
255 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
256 "spsr_mon", "spsr_und", "spsr_abt",
257 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
258 "mvfr0", "mvfr1",
259 "sctlr_rst", "sev_mailbox",
260 "DBGDIDR",
261 "DBGDSCR_INT",
262 "DBGDTRRX_INT",

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321 "dcimvac", "dcisw", "mccsw",
322 "dccmvau",
323 "nsacr",
324 "vbar", "mvbar", "isr", "fceidr", "l2latency",
325 "crn15",
326 "nop", "raz"
327 };
328
329 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
330 "The miscRegName array and NUM_MISCREGS are inconsistent.");
331
328 BitUnion32(CPSR)
329 Bitfield<31,30> nz;
330 Bitfield<29> c;
331 Bitfield<28> v;
332 Bitfield<27> q;
333 Bitfield<26,25> it1;
334 Bitfield<24> j;
335 Bitfield<19, 16> ge;

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333 Bitfield<31,30> nz;
334 Bitfield<29> c;
335 Bitfield<28> v;
336 Bitfield<27> q;
337 Bitfield<26,25> it1;
338 Bitfield<24> j;
339 Bitfield<19, 16> ge;

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