miscregs.hh (9051:1554b7722990) miscregs.hh (9130:8423aa8c2216)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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524 Bitfield<21> eccandParityEnable;
525 Bitfield<22> reserved_22;
526 Bitfield<23> interptCtrlPresent;
527 Bitfield<25,24> numCPUs;
528 Bitfield<30,26> reserved_30_26;
529 Bitfield<31> l2rstDISABLE_monitor;
530 EndBitUnion(L2CTLR)
531
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 515 unchanged lines hidden (view full) ---

524 Bitfield<21> eccandParityEnable;
525 Bitfield<22> reserved_22;
526 Bitfield<23> interptCtrlPresent;
527 Bitfield<25,24> numCPUs;
528 Bitfield<30,26> reserved_30_26;
529 Bitfield<31> l2rstDISABLE_monitor;
530 EndBitUnion(L2CTLR)
531
532 BitUnion32(CTR)
533 Bitfield<3,0> iCacheLineSize;
534 Bitfield<13,4> raz_13_4;
535 Bitfield<15,14> l1IndexPolicy;
536 Bitfield<19,16> dCacheLineSize;
537 Bitfield<23,20> erg;
538 Bitfield<27,24> cwg;
539 Bitfield<28> raz_28;
540 Bitfield<31,29> format;
541 EndBitUnion(CTR)
532}
533
534#endif // __ARCH_ARM_MISCREGS_HH__
542}
543
544#endif // __ARCH_ARM_MISCREGS_HH__