| miscregs.hh (8902:75b524b64c28) | miscregs.hh (9051:1554b7722990) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 337 unchanged lines hidden (view full) --- 346 // integer register to allow renaming. 347 static const uint32_t CondCodesMask = 0xF00F0000; 348 static const uint32_t CpsrMaskQ = 0x08000000; 349 350 BitUnion32(SCTLR) 351 Bitfield<31> ie; // Instruction endianness 352 Bitfield<30> te; // Thumb Exception Enable 353 Bitfield<29> afe; // Access flag enable | 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 337 unchanged lines hidden (view full) --- 346 // integer register to allow renaming. 347 static const uint32_t CondCodesMask = 0xF00F0000; 348 static const uint32_t CpsrMaskQ = 0x08000000; 349 350 BitUnion32(SCTLR) 351 Bitfield<31> ie; // Instruction endianness 352 Bitfield<30> te; // Thumb Exception Enable 353 Bitfield<29> afe; // Access flag enable |
| 354 Bitfield<28> tre; // TEX Remap bit | 354 Bitfield<28> tre; // TEX Remap bit |
| 355 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 356 Bitfield<25> ee; // Exception Endianness bit 357 Bitfield<24> ve; // Interrupt vectors enable 358 Bitfield<23> xp; // Extended page table enable bit 359 Bitfield<22> u; // Alignment (now unused) 360 Bitfield<21> fi; // Fast interrupts configuration enable 361 Bitfield<19> dz; // Divide by Zero fault enable bit 362 Bitfield<18> rao2;// Read as one 363 Bitfield<17> br; // Background region bit 364 Bitfield<16> rao3;// Read as one 365 Bitfield<14> rr; // Round robin cache replacement 366 Bitfield<13> v; // Base address for exception vectors 367 Bitfield<12> i; // instruction cache enable 368 Bitfield<11> z; // branch prediction enable bit 369 Bitfield<10> sw; // Enable swp/swpb 370 Bitfield<9,8> rs; // deprecated protection bits 371 Bitfield<6,3> rao4;// Read as one | 355 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 356 Bitfield<25> ee; // Exception Endianness bit 357 Bitfield<24> ve; // Interrupt vectors enable 358 Bitfield<23> xp; // Extended page table enable bit 359 Bitfield<22> u; // Alignment (now unused) 360 Bitfield<21> fi; // Fast interrupts configuration enable 361 Bitfield<19> dz; // Divide by Zero fault enable bit 362 Bitfield<18> rao2;// Read as one 363 Bitfield<17> br; // Background region bit 364 Bitfield<16> rao3;// Read as one 365 Bitfield<14> rr; // Round robin cache replacement 366 Bitfield<13> v; // Base address for exception vectors 367 Bitfield<12> i; // instruction cache enable 368 Bitfield<11> z; // branch prediction enable bit 369 Bitfield<10> sw; // Enable swp/swpb 370 Bitfield<9,8> rs; // deprecated protection bits 371 Bitfield<6,3> rao4;// Read as one |
| 372 Bitfield<7> b; // Endianness support (unused) | 372 Bitfield<7> b; // Endianness support (unused) |
| 373 Bitfield<2> c; // Cache enable bit 374 Bitfield<1> a; // Alignment fault checking | 373 Bitfield<2> c; // Cache enable bit 374 Bitfield<1> a; // Alignment fault checking |
| 375 Bitfield<0> m; // MMU enable bit | 375 Bitfield<0> m; // MMU enable bit |
| 376 EndBitUnion(SCTLR) 377 378 BitUnion32(CPACR) 379 Bitfield<1, 0> cp0; 380 Bitfield<3, 2> cp1; 381 Bitfield<5, 4> cp2; 382 Bitfield<7, 6> cp3; 383 Bitfield<9, 8> cp4; --- 151 unchanged lines hidden --- | 376 EndBitUnion(SCTLR) 377 378 BitUnion32(CPACR) 379 Bitfield<1, 0> cp0; 380 Bitfield<3, 2> cp1; 381 Bitfield<5, 4> cp2; 382 Bitfield<7, 6> cp3; 383 Bitfield<9, 8> cp4; --- 151 unchanged lines hidden --- |