miscregs.hh (8468:5e9530779f60) miscregs.hh (8549:7cff2156c998)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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172 MISCREG_ID_ISAR2,
173 MISCREG_ID_ISAR3,
174 MISCREG_ID_ISAR4,
175 MISCREG_ID_ISAR5,
176 MISCREG_CPSR_MODE,
177 MISCREG_LOCKFLAG,
178 MISCREG_LOCKADDR,
179 MISCREG_ID_PFR1,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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172 MISCREG_ID_ISAR2,
173 MISCREG_ID_ISAR3,
174 MISCREG_ID_ISAR4,
175 MISCREG_ID_ISAR5,
176 MISCREG_CPSR_MODE,
177 MISCREG_LOCKFLAG,
178 MISCREG_LOCKADDR,
179 MISCREG_ID_PFR1,
180 MISCREG_L2CTLR,
180 MISCREG_CP15_UNIMP_START,
181 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
182 MISCREG_ID_DFR0,
183 MISCREG_ID_AFR0,
184 MISCREG_ID_MMFR1,
185 MISCREG_AIDR,
186 MISCREG_ADFSR,
187 MISCREG_AIFSR,

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233 "v2powpr", "v2powpw", "v2powur", "v2powuw",
234 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr",
235 "pmcntenset", "pmcntenclr", "pmovsr",
236 "pmswinc", "pmselr", "pmceid0",
237 "pmceid1", "pmc_other", "pmxevcntr",
238 "pmuserenr", "pmintenset", "pmintenclr",
239 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
240 "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
181 MISCREG_CP15_UNIMP_START,
182 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
183 MISCREG_ID_DFR0,
184 MISCREG_ID_AFR0,
185 MISCREG_ID_MMFR1,
186 MISCREG_AIDR,
187 MISCREG_ADFSR,
188 MISCREG_AIFSR,

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234 "v2powpr", "v2powpw", "v2powur", "v2powuw",
235 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr",
236 "pmcntenset", "pmcntenclr", "pmovsr",
237 "pmswinc", "pmselr", "pmceid0",
238 "pmceid1", "pmc_other", "pmxevcntr",
239 "pmuserenr", "pmintenset", "pmintenclr",
240 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
241 "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
242 "l2ctlr",
241 // Unimplemented below
242 "tcmtr",
243 "id_dfr0", "id_afr0",
244 "id_mmfr1",
245 "aidr", "adfsr", "aifsr",
246 "dcimvac", "dcisw", "mccsw",
247 "dccmvau",
248 "nsacr",

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427 Bitfield<21,20> or2;
428 Bitfield<23,22> or3;
429 Bitfield<25,24> or4;
430 Bitfield<27,26> or5;
431 Bitfield<29,28> or6;
432 Bitfield<31,30> or7;
433 EndBitUnion(NMRR)
434
243 // Unimplemented below
244 "tcmtr",
245 "id_dfr0", "id_afr0",
246 "id_mmfr1",
247 "aidr", "adfsr", "aifsr",
248 "dcimvac", "dcisw", "mccsw",
249 "dccmvau",
250 "nsacr",

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429 Bitfield<21,20> or2;
430 Bitfield<23,22> or3;
431 Bitfield<25,24> or4;
432 Bitfield<27,26> or5;
433 Bitfield<29,28> or6;
434 Bitfield<31,30> or7;
435 EndBitUnion(NMRR)
436
437 BitUnion32(L2CTLR)
438 Bitfield<2,0> sataRAMLatency;
439 Bitfield<4,3> reserved_4_3;
440 Bitfield<5> dataRAMSetup;
441 Bitfield<8,6> tagRAMLatency;
442 Bitfield<9> tagRAMSetup;
443 Bitfield<11,10> dataRAMSlice;
444 Bitfield<12> tagRAMSlice;
445 Bitfield<20,13> reserved_20_13;
446 Bitfield<21> eccandParityEnable;
447 Bitfield<22> reserved_22;
448 Bitfield<23> interptCtrlPresent;
449 Bitfield<25,24> numCPUs;
450 Bitfield<30,26> reserved_30_26;
451 Bitfield<31> l2rstDISABLE_monitor;
452 EndBitUnion(L2CTLR)
453
435};
436
437#endif // __ARCH_ARM_MISCREGS_HH__
454};
455
456#endif // __ARCH_ARM_MISCREGS_HH__