miscregs.hh (8302:9f23d01421de) miscregs.hh (8303:5a95f1d2494e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 237 unchanged lines hidden (view full) ---

246 "dcimvac", "dcisw", "mccsw",
247 "dccmvau",
248 "nsacr",
249 "vbar", "mvbar", "isr", "fceidr", "l2latency",
250 "nop", "raz"
251 };
252
253 BitUnion32(CPSR)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 237 unchanged lines hidden (view full) ---

246 "dcimvac", "dcisw", "mccsw",
247 "dccmvau",
248 "nsacr",
249 "vbar", "mvbar", "isr", "fceidr", "l2latency",
250 "nop", "raz"
251 };
252
253 BitUnion32(CPSR)
254 Bitfield<31> n;
255 Bitfield<30> z;
254 Bitfield<31,30> nz;
256 Bitfield<29> c;
257 Bitfield<28> v;
258 Bitfield<27> q;
259 Bitfield<26,25> it1;
260 Bitfield<24> j;
261 Bitfield<19, 16> ge;
262 Bitfield<15,10> it2;
263 Bitfield<9> e;
264 Bitfield<8> a;
265 Bitfield<7> i;
266 Bitfield<6> f;
267 Bitfield<5> t;
268 Bitfield<4, 0> mode;
269 EndBitUnion(CPSR)
270
271 // This mask selects bits of the CPSR that actually go in the CondCodes
272 // integer register to allow renaming.
273 static const uint32_t CondCodesMask = 0xF00F0000;
255 Bitfield<29> c;
256 Bitfield<28> v;
257 Bitfield<27> q;
258 Bitfield<26,25> it1;
259 Bitfield<24> j;
260 Bitfield<19, 16> ge;
261 Bitfield<15,10> it2;
262 Bitfield<9> e;
263 Bitfield<8> a;
264 Bitfield<7> i;
265 Bitfield<6> f;
266 Bitfield<5> t;
267 Bitfield<4, 0> mode;
268 EndBitUnion(CPSR)
269
270 // This mask selects bits of the CPSR that actually go in the CondCodes
271 // integer register to allow renaming.
272 static const uint32_t CondCodesMask = 0xF00F0000;
274 static const uint32_t CondCodesMaskF = 0xF0000000;
275 static const uint32_t CpsrMaskQ = 0x08000000;
273 static const uint32_t CpsrMaskQ = 0x08000000;
276 static const uint32_t CondCodesMaskGE = 0x000F0000;
277
278 BitUnion32(SCTLR)
279 Bitfield<31> ie; // Instruction endianness
280 Bitfield<30> te; // Thumb Exception Enable
281 Bitfield<29> afe; // Access flag enable
282 Bitfield<28> tre; // TEX Remap bit
283 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
284 Bitfield<25> ee; // Exception Endianness bit

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275 BitUnion32(SCTLR)
276 Bitfield<31> ie; // Instruction endianness
277 Bitfield<30> te; // Thumb Exception Enable
278 Bitfield<29> afe; // Access flag enable
279 Bitfield<28> tre; // TEX Remap bit
280 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
281 Bitfield<25> ee; // Exception Endianness bit

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