miscregs.hh (7762:6e399e631a43) miscregs.hh (7783:9b880b40ac10)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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73 MISCREG_SPSR_IRQ,
74 MISCREG_SPSR_SVC,
75 MISCREG_SPSR_MON,
76 MISCREG_SPSR_UND,
77 MISCREG_SPSR_ABT,
78 MISCREG_FPSR,
79 MISCREG_FPSID,
80 MISCREG_FPSCR,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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73 MISCREG_SPSR_IRQ,
74 MISCREG_SPSR_SVC,
75 MISCREG_SPSR_MON,
76 MISCREG_SPSR_UND,
77 MISCREG_SPSR_ABT,
78 MISCREG_FPSR,
79 MISCREG_FPSID,
80 MISCREG_FPSCR,
81 MISCREG_FPSCR_QC, // Cumulative saturation flag
82 MISCREG_FPSCR_EXC, // Cumulative FP exception flags
81 MISCREG_FPEXC,
82 MISCREG_MVFR0,
83 MISCREG_MVFR1,
84 MISCREG_SCTLR_RST,
85 MISCREG_SEV_MAILBOX,
86
87 // CP15 registers
88 MISCREG_CP15_START,

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201 };
202
203 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
204 unsigned crm, unsigned opc2);
205
206 const char * const miscRegName[NUM_MISCREGS] = {
207 "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
208 "spsr_mon", "spsr_und", "spsr_abt",
83 MISCREG_FPEXC,
84 MISCREG_MVFR0,
85 MISCREG_MVFR1,
86 MISCREG_SCTLR_RST,
87 MISCREG_SEV_MAILBOX,
88
89 // CP15 registers
90 MISCREG_CP15_START,

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203 };
204
205 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
206 unsigned crm, unsigned opc2);
207
208 const char * const miscRegName[NUM_MISCREGS] = {
209 "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
210 "spsr_mon", "spsr_und", "spsr_abt",
209 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
211 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
212 "mvfr0", "mvfr1",
210 "sctlr_rst", "sev_mailbox",
211 "sctlr", "dccisw", "dccimvac", "dccmvac",
212 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
213 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
214 "clidr", "ccsidr", "csselr",
215 "icialluis", "iciallu", "icimvau",
216 "bpimva", "bpiallis", "bpiall",
217 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",

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357 Bitfield<28> v;
358 Bitfield<29> c;
359 Bitfield<30> z;
360 Bitfield<31> n;
361 EndBitUnion(FPSCR)
362
363 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
364 // integer register to allow renaming.
213 "sctlr_rst", "sev_mailbox",
214 "sctlr", "dccisw", "dccimvac", "dccmvac",
215 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
216 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
217 "clidr", "ccsidr", "csselr",
218 "icialluis", "iciallu", "icimvau",
219 "bpimva", "bpiallis", "bpiall",
220 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",

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360 Bitfield<28> v;
361 Bitfield<29> c;
362 Bitfield<30> z;
363 Bitfield<31> n;
364 EndBitUnion(FPSCR)
365
366 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
367 // integer register to allow renaming.
365 static const uint32_t FpCondCodesMask = 0xF800009F;
368 static const uint32_t FpCondCodesMask = 0xF0000000;
369 // This mask selects the cumulative FP exception flags of the FPSCR.
370 static const uint32_t FpscrExcMask = 0x0000009F;
371 // This mask selects the cumulative saturation flag of the FPSCR.
372 static const uint32_t FpscrQcMask = 0x08000000;
366
367 BitUnion32(FPEXC)
368 Bitfield<31> ex;
369 Bitfield<30> en;
370 Bitfield<29, 0> subArchDefined;
371 EndBitUnion(FPEXC)
372
373 BitUnion32(MVFR0)

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374 BitUnion32(FPEXC)
375 Bitfield<31> ex;
376 Bitfield<30> en;
377 Bitfield<29, 0> subArchDefined;
378 EndBitUnion(FPEXC)
379
380 BitUnion32(MVFR0)

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