miscregs.hh (7640:5286a8a469c5) miscregs.hh (7643:775ccd204013)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 340 unchanged lines hidden (view full) ---

349 Bitfield<26> ahp;
350 Bitfield<27> qc;
351 Bitfield<28> v;
352 Bitfield<29> c;
353 Bitfield<30> z;
354 Bitfield<31> n;
355 EndBitUnion(FPSCR)
356
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 340 unchanged lines hidden (view full) ---

349 Bitfield<26> ahp;
350 Bitfield<27> qc;
351 Bitfield<28> v;
352 Bitfield<29> c;
353 Bitfield<30> z;
354 Bitfield<31> n;
355 EndBitUnion(FPSCR)
356
357 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
358 // integer register to allow renaming.
359 static const uint32_t FpCondCodesMask = 0xF800009F;
360
357 BitUnion32(FPEXC)
358 Bitfield<31> ex;
359 Bitfield<30> en;
360 Bitfield<29, 0> subArchDefined;
361 EndBitUnion(FPEXC)
362
363 BitUnion32(MVFR0)
364 Bitfield<3, 0> advSimdRegisters;

--- 65 unchanged lines hidden --- 		361 BitUnion32(FPEXC)
362 Bitfield<31> ex;
363 Bitfield<30> en;
364 Bitfield<29, 0> subArchDefined;
365 EndBitUnion(FPEXC)
366
367 BitUnion32(MVFR0)
368 Bitfield<3, 0> advSimdRegisters;

--- 65 unchanged lines hidden ---