miscregs.hh (7583:665d71561298) | miscregs.hh (7640:5286a8a469c5) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 340 unchanged lines hidden (view full) --- 349 Bitfield<26> ahp; 350 Bitfield<27> qc; 351 Bitfield<28> v; 352 Bitfield<29> c; 353 Bitfield<30> z; 354 Bitfield<31> n; 355 EndBitUnion(FPSCR) 356 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 340 unchanged lines hidden (view full) --- 349 Bitfield<26> ahp; 350 Bitfield<27> qc; 351 Bitfield<28> v; 352 Bitfield<29> c; 353 Bitfield<30> z; 354 Bitfield<31> n; 355 EndBitUnion(FPSCR) 356 |
357 BitUnion32(FPEXC) 358 Bitfield<31> ex; 359 Bitfield<30> en; 360 Bitfield<29, 0> subArchDefined; 361 EndBitUnion(FPEXC) 362 |
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357 BitUnion32(MVFR0) 358 Bitfield<3, 0> advSimdRegisters; 359 Bitfield<7, 4> singlePrecision; 360 Bitfield<11, 8> doublePrecision; 361 Bitfield<15, 12> vfpExceptionTrapping; 362 Bitfield<19, 16> divide; 363 Bitfield<23, 20> squareRoot; 364 Bitfield<27, 24> shortVectors; --- 59 unchanged lines hidden --- | 363 BitUnion32(MVFR0) 364 Bitfield<3, 0> advSimdRegisters; 365 Bitfield<7, 4> singlePrecision; 366 Bitfield<11, 8> doublePrecision; 367 Bitfield<15, 12> vfpExceptionTrapping; 368 Bitfield<19, 16> divide; 369 Bitfield<23, 20> squareRoot; 370 Bitfield<27, 24> shortVectors; --- 59 unchanged lines hidden --- |