miscregs.hh (7406:ddc26bd4ea7d) miscregs.hh (7408:ee6949c5bb5b)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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62 COND_GT, // 12
63 COND_LE, // 13
64 COND_AL, // 14
65 COND_UC // 15
66 };
67
68 enum MiscRegIndex {
69 MISCREG_CPSR = 0,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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62 COND_GT, // 12
63 COND_LE, // 13
64 COND_AL, // 14
65 COND_UC // 15
66 };
67
68 enum MiscRegIndex {
69 MISCREG_CPSR = 0,
70 MISCREG_ITSTATE,
70 MISCREG_SPSR,
71 MISCREG_SPSR_FIQ,
72 MISCREG_SPSR_IRQ,
73 MISCREG_SPSR_SVC,
74 MISCREG_SPSR_MON,
75 MISCREG_SPSR_UND,
76 MISCREG_SPSR_ABT,
77 MISCREG_FPSR,

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184
185 NUM_MISCREGS
186 };
187
188 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
189 unsigned crm, unsigned opc2);
190
191 const char * const miscRegName[NUM_MISCREGS] = {
71 MISCREG_SPSR,
72 MISCREG_SPSR_FIQ,
73 MISCREG_SPSR_IRQ,
74 MISCREG_SPSR_SVC,
75 MISCREG_SPSR_MON,
76 MISCREG_SPSR_UND,
77 MISCREG_SPSR_ABT,
78 MISCREG_FPSR,

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185
186 NUM_MISCREGS
187 };
188
189 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
190 unsigned crm, unsigned opc2);
191
192 const char * const miscRegName[NUM_MISCREGS] = {
192 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
193 "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
193 "spsr_mon", "spsr_und", "spsr_abt",
194 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
195 "sctlr_rst", "sev_mailbox",
196 "sctlr", "dccisw", "dccimvac", "dccmvac",
197 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
198 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
199 "clidr", "ccsidr", "csselr",
200 "icialluis", "iciallu", "icimvau",

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236 Bitfield<9> e;
237 Bitfield<8> a;
238 Bitfield<7> i;
239 Bitfield<6> f;
240 Bitfield<5> t;
241 Bitfield<4, 0> mode;
242 EndBitUnion(CPSR)
243
194 "spsr_mon", "spsr_und", "spsr_abt",
195 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
196 "sctlr_rst", "sev_mailbox",
197 "sctlr", "dccisw", "dccimvac", "dccmvac",
198 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
199 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
200 "clidr", "ccsidr", "csselr",
201 "icialluis", "iciallu", "icimvau",

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237 Bitfield<9> e;
238 Bitfield<8> a;
239 Bitfield<7> i;
240 Bitfield<6> f;
241 Bitfield<5> t;
242 Bitfield<4, 0> mode;
243 EndBitUnion(CPSR)
244
245 BitUnion8(ITSTATE)
246 Bitfield<7, 4> cond;
247 Bitfield<3, 0> mask;
248 // Bitfields for moving to/from CPSR
249 Bitfield<7, 2> top6;
250 Bitfield<1, 0> bottom2;
251 EndBitUnion(ITSTATE)
252
244 // This mask selects bits of the CPSR that actually go in the CondCodes
245 // integer register to allow renaming.
246 static const uint32_t CondCodesMask = 0xF80F0000;
247
248 BitUnion32(SCTLR)
249 Bitfield<31> ie; // Instruction endianness
250 Bitfield<30> te; // Thumb Exception Enable
251 Bitfield<29> afe; // Access flag enable

--- 144 unchanged lines hidden --- 		253 // This mask selects bits of the CPSR that actually go in the CondCodes
254 // integer register to allow renaming.
255 static const uint32_t CondCodesMask = 0xF80F0000;
256
257 BitUnion32(SCTLR)
258 Bitfield<31> ie; // Instruction endianness
259 Bitfield<30> te; // Thumb Exception Enable
260 Bitfield<29> afe; // Access flag enable

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