miscregs.hh (7404:bfc74724914e) miscregs.hh (7406:ddc26bd4ea7d)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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129 MISCREG_IFSR,
130 MISCREG_DFAR,
131 MISCREG_IFAR,
132 MISCREG_MPIDR,
133 MISCREG_PRRR,
134 MISCREG_NMRR,
135 MISCREG_TTBCR,
136 MISCREG_ID_PFR0,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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129 MISCREG_IFSR,
130 MISCREG_DFAR,
131 MISCREG_IFAR,
132 MISCREG_MPIDR,
133 MISCREG_PRRR,
134 MISCREG_NMRR,
135 MISCREG_TTBCR,
136 MISCREG_ID_PFR0,
137 MISCREG_CTR,
138 MISCREG_SCR,
139 MISCREG_SDER,
137 MISCREG_CP15_UNIMP_START,
140 MISCREG_CP15_UNIMP_START,
138 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
139 MISCREG_TCMTR,
141 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
140 MISCREG_ID_PFR1,
141 MISCREG_ID_DFR0,
142 MISCREG_ID_AFR0,
143 MISCREG_ID_MMFR0,
144 MISCREG_ID_MMFR1,
145 MISCREG_ID_MMFR2,
146 MISCREG_ID_MMFR3,
147 MISCREG_ID_ISAR0,

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154 MISCREG_AIDR,
155 MISCREG_ACTLR,
156 MISCREG_ADFSR,
157 MISCREG_AIFSR,
158 MISCREG_DCIMVAC,
159 MISCREG_DCISW,
160 MISCREG_MCCSW,
161 MISCREG_DCCMVAU,
142 MISCREG_ID_PFR1,
143 MISCREG_ID_DFR0,
144 MISCREG_ID_AFR0,
145 MISCREG_ID_MMFR0,
146 MISCREG_ID_MMFR1,
147 MISCREG_ID_MMFR2,
148 MISCREG_ID_MMFR3,
149 MISCREG_ID_ISAR0,

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156 MISCREG_AIDR,
157 MISCREG_ACTLR,
158 MISCREG_ADFSR,
159 MISCREG_AIFSR,
160 MISCREG_DCIMVAC,
161 MISCREG_DCISW,
162 MISCREG_MCCSW,
163 MISCREG_DCCMVAU,
162 MISCREG_SCR,
163 MISCREG_SDER,
164 MISCREG_NSACR,
165 MISCREG_V2PCWPR,
166 MISCREG_V2PCWPW,
167 MISCREG_V2PCWUR,
168 MISCREG_V2PCWUW,
169 MISCREG_V2POWPR,
170 MISCREG_V2POWPW,
171 MISCREG_V2POWUR,

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200 "icialluis", "iciallu", "icimvau",
201 "bpimva", "bpiallis", "bpiall",
202 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
203 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
204 "itlbiall", "itlbimva", "itlbiasid",
205 "dtlbiall", "dtlbimva", "dtlbiasid",
206 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
207 "dfsr", "ifsr", "dfar", "ifar", "mpidr",
164 MISCREG_NSACR,
165 MISCREG_V2PCWPR,
166 MISCREG_V2PCWPW,
167 MISCREG_V2PCWUR,
168 MISCREG_V2PCWUW,
169 MISCREG_V2POWPR,
170 MISCREG_V2POWPW,
171 MISCREG_V2POWUR,

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200 "icialluis", "iciallu", "icimvau",
201 "bpimva", "bpiallis", "bpiall",
202 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
203 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
204 "itlbiall", "itlbimva", "itlbiasid",
205 "dtlbiall", "dtlbimva", "dtlbiasid",
206 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
207 "dfsr", "ifsr", "dfar", "ifar", "mpidr",
208 "prrr", "nmrr", "ttbcr", "id_pfr0",
208 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr"
209 "scr", "sder"
209 // Unimplemented below
210 // Unimplemented below
210 "ctr", "tcmtr",
211 "tcmtr",
211 "id_pfr1", "id_dfr0", "id_afr0",
212 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
213 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
214 "par", "aidr", "actlr",
215 "adfsr", "aifsr",
216 "dcimvac", "dcisw", "mccsw",
217 "dccmvau",
212 "id_pfr1", "id_dfr0", "id_afr0",
213 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
214 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
215 "par", "aidr", "actlr",
216 "adfsr", "aifsr",
217 "dcimvac", "dcisw", "mccsw",
218 "dccmvau",
218 "scr", "sder", "nsacr",
219 "nsacr",
219 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
220 "v2powpr", "v2powpw", "v2powur", "v2powuw",
221 "vbar", "mvbar", "isr", "fceidr",
222 "nop", "raz"
223 };
224
225 BitUnion32(CPSR)
226 Bitfield<31> n;

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247 BitUnion32(SCTLR)
248 Bitfield<31> ie; // Instruction endianness
249 Bitfield<30> te; // Thumb Exception Enable
250 Bitfield<29> afe; // Access flag enable
251 Bitfield<28> tre; // TEX Remap bit
252 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
253 Bitfield<25> ee; // Exception Endianness bit
254 Bitfield<24> ve; // Interrupt vectors enable
220 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
221 "v2powpr", "v2powpw", "v2powur", "v2powuw",
222 "vbar", "mvbar", "isr", "fceidr",
223 "nop", "raz"
224 };
225
226 BitUnion32(CPSR)
227 Bitfield<31> n;

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248 BitUnion32(SCTLR)
249 Bitfield<31> ie; // Instruction endianness
250 Bitfield<30> te; // Thumb Exception Enable
251 Bitfield<29> afe; // Access flag enable
252 Bitfield<28> tre; // TEX Remap bit
253 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
254 Bitfield<25> ee; // Exception Endianness bit
255 Bitfield<24> ve; // Interrupt vectors enable
255 Bitfield<23> rao1;// Read as one
256 Bitfield<23> xp; // Extended page table enable bit
256 Bitfield<22> u; // Alignment (now unused)
257 Bitfield<21> fi; // Fast interrupts configuration enable
258 Bitfield<19> dz; // Divide by Zero fault enable bit
259 Bitfield<18> rao2;// Read as one
260 Bitfield<17> br; // Background region bit
261 Bitfield<16> rao3;// Read as one
262 Bitfield<14> rr; // Round robin cache replacement
263 Bitfield<13> v; // Base address for exception vectors
264 Bitfield<12> i; // instruction cache enable
265 Bitfield<11> z; // branch prediction enable bit
266 Bitfield<10> sw; // Enable swp/swpb
257 Bitfield<22> u; // Alignment (now unused)
258 Bitfield<21> fi; // Fast interrupts configuration enable
259 Bitfield<19> dz; // Divide by Zero fault enable bit
260 Bitfield<18> rao2;// Read as one
261 Bitfield<17> br; // Background region bit
262 Bitfield<16> rao3;// Read as one
263 Bitfield<14> rr; // Round robin cache replacement
264 Bitfield<13> v; // Base address for exception vectors
265 Bitfield<12> i; // instruction cache enable
266 Bitfield<11> z; // branch prediction enable bit
267 Bitfield<10> sw; // Enable swp/swpb
268 Bitfield<9,8> rs; // deprecated protection bits
267 Bitfield<6,3> rao4;// Read as one
268 Bitfield<7> b; // Endianness support (unused)
269 Bitfield<2> c; // Cache enable bit
270 Bitfield<1> a; // Alignment fault checking
271 Bitfield<0> m; // MMU enable bit
272 EndBitUnion(SCTLR)
273
274 BitUnion32(CPACR)

--- 119 unchanged lines hidden --- 		269 Bitfield<6,3> rao4;// Read as one
270 Bitfield<7> b; // Endianness support (unused)
271 Bitfield<2> c; // Cache enable bit
272 Bitfield<1> a; // Alignment fault checking
273 Bitfield<0> m; // MMU enable bit
274 EndBitUnion(SCTLR)
275
276 BitUnion32(CPACR)

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