miscregs.hh (7376:3b781776b2d9) miscregs.hh (7383:0edb04052953)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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315 Bitfield<25> dn;
316 Bitfield<26> ahp;
317 Bitfield<27> qc;
318 Bitfield<28> v;
319 Bitfield<29> c;
320 Bitfield<30> z;
321 Bitfield<31> n;
322 EndBitUnion(FPSCR)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 306 unchanged lines hidden (view full) ---

315 Bitfield<25> dn;
316 Bitfield<26> ahp;
317 Bitfield<27> qc;
318 Bitfield<28> v;
319 Bitfield<29> c;
320 Bitfield<30> z;
321 Bitfield<31> n;
322 EndBitUnion(FPSCR)
323
324 BitUnion32(MVFR0)
325 Bitfield<3, 0> advSimdRegisters;
326 Bitfield<7, 4> singlePrecision;
327 Bitfield<11, 8> doublePrecision;
328 Bitfield<15, 12> vfpExceptionTrapping;
329 Bitfield<19, 16> divide;
330 Bitfield<23, 20> squareRoot;
331 Bitfield<27, 24> shortVectors;
332 Bitfield<31, 28> roundingModes;
333 EndBitUnion(MVFR0)
334
335 BitUnion32(MVFR1)
336 Bitfield<3, 0> flushToZero;
337 Bitfield<7, 4> defaultNaN;
338 Bitfield<11, 8> advSimdLoadStore;
339 Bitfield<15, 12> advSimdInteger;
340 Bitfield<19, 16> advSimdSinglePrecision;
341 Bitfield<23, 20> advSimdHalfPrecision;
342 Bitfield<27, 24> vfpHalfPrecision;
343 Bitfield<31, 28> raz;
344 EndBitUnion(MVFR1)
323};
324
325#endif // __ARCH_ARM_MISCREGS_HH__
345};
346
347#endif // __ARCH_ARM_MISCREGS_HH__