miscregs.hh (7362:9ea92e0eb4a9) miscregs.hh (7376:3b781776b2d9)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 280 unchanged lines hidden (view full) ---

289
290 BitUnion32(FSR)
291 Bitfield<3, 0> fsLow;
292 Bitfield<7, 4> domain;
293 Bitfield<10> fsHigh;
294 Bitfield<11> wnr;
295 Bitfield<12> ext;
296 EndBitUnion(FSR)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 280 unchanged lines hidden (view full) ---

289
290 BitUnion32(FSR)
291 Bitfield<3, 0> fsLow;
292 Bitfield<7, 4> domain;
293 Bitfield<10> fsHigh;
294 Bitfield<11> wnr;
295 Bitfield<12> ext;
296 EndBitUnion(FSR)
297
298 BitUnion32(FPSCR)
299 Bitfield<0> ioc;
300 Bitfield<1> dzc;
301 Bitfield<2> ofc;
302 Bitfield<3> ufc;
303 Bitfield<4> ixc;
304 Bitfield<7> idc;
305 Bitfield<8> ioe;
306 Bitfield<9> dze;
307 Bitfield<10> ofe;
308 Bitfield<11> ufe;
309 Bitfield<12> ixe;
310 Bitfield<15> ide;
311 Bitfield<18, 16> len;
312 Bitfield<21, 20> stride;
313 Bitfield<23, 22> rMode;
314 Bitfield<24> fz;
315 Bitfield<25> dn;
316 Bitfield<26> ahp;
317 Bitfield<27> qc;
318 Bitfield<28> v;
319 Bitfield<29> c;
320 Bitfield<30> z;
321 Bitfield<31> n;
322 EndBitUnion(FPSCR)
297};
298
299#endif // __ARCH_ARM_MISCREGS_HH__
323};
324
325#endif // __ARCH_ARM_MISCREGS_HH__