| miscregs.hh (7355:8d9b757b3583) | miscregs.hh (7360:49a1e8b1632f) |
|---|---|
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 227 unchanged lines hidden (view full) --- 236 Bitfield<4, 0> mode; 237 EndBitUnion(CPSR) 238 239 // This mask selects bits of the CPSR that actually go in the CondCodes 240 // integer register to allow renaming. 241 static const uint32_t CondCodesMask = 0xF80F0000; 242 243 BitUnion32(SCTLR) | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 227 unchanged lines hidden (view full) --- 236 Bitfield<4, 0> mode; 237 EndBitUnion(CPSR) 238 239 // This mask selects bits of the CPSR that actually go in the CondCodes 240 // integer register to allow renaming. 241 static const uint32_t CondCodesMask = 0xF80F0000; 242 243 BitUnion32(SCTLR) |
| 244 Bitfield<31> ie; // Instruction endianness |
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| 244 Bitfield<30> te; // Thumb Exception Enable 245 Bitfield<29> afe; // Access flag enable 246 Bitfield<28> tre; // TEX Remap bit 247 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 248 Bitfield<25> ee; // Exception Endianness bit 249 Bitfield<24> ve; // Interrupt vectors enable 250 Bitfield<23> rao1;// Read as one 251 Bitfield<22> u; // Alignment (now unused) 252 Bitfield<21> fi; // Fast interrupts configuration enable | 245 Bitfield<30> te; // Thumb Exception Enable 246 Bitfield<29> afe; // Access flag enable 247 Bitfield<28> tre; // TEX Remap bit 248 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 249 Bitfield<25> ee; // Exception Endianness bit 250 Bitfield<24> ve; // Interrupt vectors enable 251 Bitfield<23> rao1;// Read as one 252 Bitfield<22> u; // Alignment (now unused) 253 Bitfield<21> fi; // Fast interrupts configuration enable |
| 254 Bitfield<19> dz; // Divide by Zero fault enable bit |
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| 253 Bitfield<18> rao2;// Read as one | 255 Bitfield<18> rao2;// Read as one |
| 254 Bitfield<17> ha; // Hardware access flag enable | 256 Bitfield<17> br; // Background region bit |
| 255 Bitfield<16> rao3;// Read as one 256 Bitfield<14> rr; // Round robin cache replacement 257 Bitfield<13> v; // Base address for exception vectors 258 Bitfield<12> i; // instruction cache enable 259 Bitfield<11> z; // branch prediction enable bit 260 Bitfield<10> sw; // Enable swp/swpb 261 Bitfield<6,3> rao4;// Read as one 262 Bitfield<7> b; // Endianness support (unused) --- 26 unchanged lines hidden --- | 257 Bitfield<16> rao3;// Read as one 258 Bitfield<14> rr; // Round robin cache replacement 259 Bitfield<13> v; // Base address for exception vectors 260 Bitfield<12> i; // instruction cache enable 261 Bitfield<11> z; // branch prediction enable bit 262 Bitfield<10> sw; // Enable swp/swpb 263 Bitfield<6,3> rao4;// Read as one 264 Bitfield<7> b; // Endianness support (unused) --- 26 unchanged lines hidden --- |