miscregs.hh (7350:41e3ee23125e) miscregs.hh (7351:d90afcb8724e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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100 MISCREG_CCSIDR,
101 MISCREG_CSSELR,
102 MISCREG_ICIALLUIS,
103 MISCREG_ICIALLU,
104 MISCREG_ICIMVAU,
105 MISCREG_BPIMVA,
106 MISCREG_BPIALLIS,
107 MISCREG_BPIALL,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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100 MISCREG_CCSIDR,
101 MISCREG_CSSELR,
102 MISCREG_ICIALLUIS,
103 MISCREG_ICIALLU,
104 MISCREG_ICIMVAU,
105 MISCREG_BPIMVA,
106 MISCREG_BPIALLIS,
107 MISCREG_BPIALL,
108 MISCREG_MPUIR,
109 MISCREG_MIDR,
108 MISCREG_MIDR,
110 MISCREG_RGNR,
111 MISCREG_DRBAR,
112 MISCREG_DRACR,
113 MISCREG_DRSR,
114 MISCREG_CP15_UNIMP_START,
115 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
109 MISCREG_CP15_UNIMP_START,
110 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
111 MISCREG_TLBTR,
116 MISCREG_TCMTR,
117 MISCREG_MPIDR,
118 MISCREG_ID_PFR0,
119 MISCREG_ID_PFR1,
120 MISCREG_ID_DFR0,
121 MISCREG_ID_AFR0,
122 MISCREG_ID_MMFR0,
123 MISCREG_ID_MMFR1,
124 MISCREG_ID_MMFR2,
125 MISCREG_ID_MMFR3,
126 MISCREG_ID_ISAR0,
127 MISCREG_ID_ISAR1,
128 MISCREG_ID_ISAR2,
129 MISCREG_ID_ISAR3,
130 MISCREG_ID_ISAR4,
131 MISCREG_ID_ISAR5,
112 MISCREG_TCMTR,
113 MISCREG_MPIDR,
114 MISCREG_ID_PFR0,
115 MISCREG_ID_PFR1,
116 MISCREG_ID_DFR0,
117 MISCREG_ID_AFR0,
118 MISCREG_ID_MMFR0,
119 MISCREG_ID_MMFR1,
120 MISCREG_ID_MMFR2,
121 MISCREG_ID_MMFR3,
122 MISCREG_ID_ISAR0,
123 MISCREG_ID_ISAR1,
124 MISCREG_ID_ISAR2,
125 MISCREG_ID_ISAR3,
126 MISCREG_ID_ISAR4,
127 MISCREG_ID_ISAR5,
128 MISCREG_PAR,
132 MISCREG_AIDR,
133 MISCREG_ACTLR,
129 MISCREG_AIDR,
130 MISCREG_ACTLR,
131 MISCREG_DACR,
134 MISCREG_DFSR,
135 MISCREG_IFSR,
136 MISCREG_ADFSR,
137 MISCREG_AIFSR,
138 MISCREG_DFAR,
139 MISCREG_IFAR,
132 MISCREG_DFSR,
133 MISCREG_IFSR,
134 MISCREG_ADFSR,
135 MISCREG_AIFSR,
136 MISCREG_DFAR,
137 MISCREG_IFAR,
140 MISCREG_IRBAR,
141 MISCREG_IRSR,
142 MISCREG_IRACR,
143 MISCREG_DCIMVAC,
144 MISCREG_DCISW,
145 MISCREG_MCCSW,
146 MISCREG_DCCMVAU,
138 MISCREG_DCIMVAC,
139 MISCREG_DCISW,
140 MISCREG_MCCSW,
141 MISCREG_DCCMVAU,
142 MISCREG_SCR,
143 MISCREG_SDER,
144 MISCREG_NSACR,
145 MISCREG_TTBR0,
146 MISCREG_TTBR1,
147 MISCREG_TTBCR,
148 MISCREG_V2PCWPR,
149 MISCREG_V2PCWPW,
150 MISCREG_V2PCWUR,
151 MISCREG_V2PCWUW,
152 MISCREG_V2POWPR,
153 MISCREG_V2POWPW,
154 MISCREG_V2POWUR,
155 MISCREG_V2POWUW,
156 MISCREG_TLBIALLIS,
157 MISCREG_TLBIMVAIS,
158 MISCREG_TLBIASIDIS,
159 MISCREG_TLBIMVAAIS,
160 MISCREG_ITLBIALL,
161 MISCREG_ITLBIMVA,
162 MISCREG_ITLBIASID,
163 MISCREG_DTLBIALL,
164 MISCREG_DTLBIMVA,
165 MISCREG_DTLBIASID,
166 MISCREG_TLBIALL,
167 MISCREG_TLBIMVA,
168 MISCREG_TLBIASID,
169 MISCREG_TLBIMVAA,
170 MISCREG_PRRR,
171 MISCREG_NMRR,
172 MISCREG_VBAR,
173 MISCREG_MVBAR,
174 MISCREG_ISR,
175 MISCREG_FCEIDR,
147
176
177
148 MISCREG_CP15_END,
149
150 // Dummy indices
151 MISCREG_NOP = MISCREG_CP15_END,
152 MISCREG_RAZ,
153
154 NUM_MISCREGS
155 };
156
157 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
158 unsigned crm, unsigned opc2);
159
160 const char * const miscRegName[NUM_MISCREGS] = {
161 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
162 "spsr_mon", "spsr_und", "spsr_abt",
178 MISCREG_CP15_END,
179
180 // Dummy indices
181 MISCREG_NOP = MISCREG_CP15_END,
182 MISCREG_RAZ,
183
184 NUM_MISCREGS
185 };
186
187 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
188 unsigned crm, unsigned opc2);
189
190 const char * const miscRegName[NUM_MISCREGS] = {
191 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
192 "spsr_mon", "spsr_und", "spsr_abt",
163 "fpsr", "fpsid", "fpscr", "fpexc", "sev_mailbox",
193 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
194 "sev_mailbox",
164 "sctlr", "dccisw", "dccimvac", "dccmvac",
165 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
166 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
167 "clidr", "ccsidr", "csselr",
168 "icialluis", "iciallu", "icimvau",
169 "bpimva", "bpiallis", "bpiall",
195 "sctlr", "dccisw", "dccimvac", "dccmvac",
196 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
197 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
198 "clidr", "ccsidr", "csselr",
199 "icialluis", "iciallu", "icimvau",
200 "bpimva", "bpiallis", "bpiall",
170 "mpuir", "midr", "rgnr", "drbar", "dracr", "drsr",
171 "ctr", "tcmtr", "mpidr",
201 "midr", "ctr", "tlbtr", "tcmtr", "mpidr",
172 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
173 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
174 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
202 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
203 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
204 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
175 "aidr", "actlr",
205 "par", "aidr", "actlr", "dacr",
176 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
206 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
177 "irbar", "irsr", "iracr",
178 "dcimvac", "dcisw", "mccsw",
179 "dccmvau",
207 "dcimvac", "dcisw", "mccsw",
208 "dccmvau",
209 "scr", "sder", "nsacr", "ttbr0", "ttbr1", "ttbcr",
210 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
211 "v2powpr", "v2powpw", "v2powur", "v2powuw",
212 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
213 "itlbiall", "itlbimva", "itlbiasid",
214 "dtlbiall", "dtlbimva", "dtlbiasid",
215 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
216 "prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr",
180 "nop", "raz"
181 };
182
183 BitUnion32(CPSR)
184 Bitfield<31> n;
185 Bitfield<30> z;
186 Bitfield<29> c;
187 Bitfield<28> v;

--- 63 unchanged lines hidden --- 		217 "nop", "raz"
218 };
219
220 BitUnion32(CPSR)
221 Bitfield<31> n;
222 Bitfield<30> z;
223 Bitfield<29> c;
224 Bitfield<28> v;

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