miscregs.hh (7300:3b491ad98fea) miscregs.hh (7320:6aacf11f7dbf)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 216 unchanged lines hidden (view full) ---

225 Bitfield<11> z; // branch prediction enable bit
226 Bitfield<10> sw; // Enable swp/swpb
227 Bitfield<6,3> rao4;// Read as one
228 Bitfield<7> b; // Endianness support (unused)
229 Bitfield<2> c; // Cache enable bit
230 Bitfield<1> a; // Alignment fault checking
231 Bitfield<0> m; // MMU enable bit
232 EndBitUnion(SCTLR)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 216 unchanged lines hidden (view full) ---

225 Bitfield<11> z; // branch prediction enable bit
226 Bitfield<10> sw; // Enable swp/swpb
227 Bitfield<6,3> rao4;// Read as one
228 Bitfield<7> b; // Endianness support (unused)
229 Bitfield<2> c; // Cache enable bit
230 Bitfield<1> a; // Alignment fault checking
231 Bitfield<0> m; // MMU enable bit
232 EndBitUnion(SCTLR)
233
234 BitUnion32(CPACR)
235 Bitfield<1, 0> cp0;
236 Bitfield<3, 2> cp1;
237 Bitfield<5, 4> cp2;
238 Bitfield<7, 6> cp3;
239 Bitfield<9, 8> cp4;
240 Bitfield<11, 10> cp5;
241 Bitfield<13, 12> cp6;
242 Bitfield<15, 14> cp7;
243 Bitfield<17, 16> cp8;
244 Bitfield<19, 18> cp9;
245 Bitfield<21, 20> cp10;
246 Bitfield<23, 22> cp11;
247 Bitfield<25, 24> cp12;
248 Bitfield<27, 26> cp13;
249 Bitfield<30> d32dis;
250 Bitfield<31> asedis;
251 EndBitUnion(CPACR)
233};
234
235#endif // __ARCH_ARM_MISCREGS_HH__
252};
253
254#endif // __ARCH_ARM_MISCREGS_HH__