miscregs.hh (7285:4b45e35807f2) miscregs.hh (7286:f6d759c122a9)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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92 MISCREG_CP15ISB,
93 MISCREG_CP15DSB,
94 MISCREG_CP15DMB,
95 MISCREG_CPACR,
96 MISCREG_CLIDR,
97 MISCREG_ICIALLUIS,
98 MISCREG_ICIALLU,
99 MISCREG_ICIMVAU,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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92 MISCREG_CP15ISB,
93 MISCREG_CP15DSB,
94 MISCREG_CP15DMB,
95 MISCREG_CPACR,
96 MISCREG_CLIDR,
97 MISCREG_ICIALLUIS,
98 MISCREG_ICIALLU,
99 MISCREG_ICIMVAU,
100 MISCREG_BPIMVA,
100 MISCREG_CP15_UNIMP_START,
101 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
102 MISCREG_TCMTR,
103 MISCREG_MPUIR,
104 MISCREG_MPIDR,
105 MISCREG_MIDR,
106 MISCREG_ID_PFR0,
107 MISCREG_ID_PFR1,

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131 MISCREG_IRBAR,
132 MISCREG_DRSR,
133 MISCREG_IRSR,
134 MISCREG_DRACR,
135 MISCREG_IRACR,
136 MISCREG_RGNR,
137 MISCREG_BPIALLIS,
138 MISCREG_BPIALL,
101 MISCREG_CP15_UNIMP_START,
102 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
103 MISCREG_TCMTR,
104 MISCREG_MPUIR,
105 MISCREG_MPIDR,
106 MISCREG_MIDR,
107 MISCREG_ID_PFR0,
108 MISCREG_ID_PFR1,

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132 MISCREG_IRBAR,
133 MISCREG_DRSR,
134 MISCREG_IRSR,
135 MISCREG_DRACR,
136 MISCREG_IRACR,
137 MISCREG_RGNR,
138 MISCREG_BPIALLIS,
139 MISCREG_BPIALL,
139 MISCREG_BPIMVA,
140 MISCREG_DCIMVAC,
141 MISCREG_DCISW,
142 MISCREG_MCCSW,
143 MISCREG_DCCMVAU,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices

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156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "dccisw", "dccimvac", "dccmvac",
162 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
163 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
140 MISCREG_DCIMVAC,
141 MISCREG_DCISW,
142 MISCREG_MCCSW,
143 MISCREG_DCCMVAU,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices

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156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "dccisw", "dccimvac", "dccmvac",
162 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
163 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
164 "icialluis", "iciallu", "icimvau",
164 "icialluis", "iciallu", "icimvau", "bpimva",
165 "ctr", "tcmtr", "mpuir", "mpidr", "midr",
166 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
167 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
168 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
169 "ccsidr", "aidr", "csselr", "actlr",
170 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
171 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
172 "rgnr", "bpiallis",
165 "ctr", "tcmtr", "mpuir", "mpidr", "midr",
166 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
167 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
168 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
169 "ccsidr", "aidr", "csselr", "actlr",
170 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
171 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
172 "rgnr", "bpiallis",
173 "bpiall", "bpimva", "dcimvac", "dcisw", "mccsw",
173 "bpiall", "dcimvac", "dcisw", "mccsw",
174 "dccmvau",
175 "nop", "raz"
176 };
177
178 BitUnion32(CPSR)
179 Bitfield<31> n;
180 Bitfield<30> z;
181 Bitfield<29> c;

--- 52 unchanged lines hidden --- 		174 "dccmvau",
175 "nop", "raz"
176 };
177
178 BitUnion32(CPSR)
179 Bitfield<31> n;
180 Bitfield<30> z;
181 Bitfield<29> c;

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