miscregs.hh (7276:8444b49bd88d) miscregs.hh (7285:4b45e35807f2)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81
82 // CP15 registers
83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
86 MISCREG_DCCIMVAC,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81
82 // CP15 registers
83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
86 MISCREG_DCCIMVAC,
87 MISCREG_DCCMVAC,
87 MISCREG_CONTEXTIDR,
88 MISCREG_TPIDRURW,
89 MISCREG_TPIDRURO,
90 MISCREG_TPIDRPRW,
91 MISCREG_CP15ISB,
92 MISCREG_CP15DSB,
93 MISCREG_CP15DMB,
94 MISCREG_CPACR,

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133 MISCREG_DRACR,
134 MISCREG_IRACR,
135 MISCREG_RGNR,
136 MISCREG_BPIALLIS,
137 MISCREG_BPIALL,
138 MISCREG_BPIMVA,
139 MISCREG_DCIMVAC,
140 MISCREG_DCISW,
88 MISCREG_CONTEXTIDR,
89 MISCREG_TPIDRURW,
90 MISCREG_TPIDRURO,
91 MISCREG_TPIDRPRW,
92 MISCREG_CP15ISB,
93 MISCREG_CP15DSB,
94 MISCREG_CP15DMB,
95 MISCREG_CPACR,

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134 MISCREG_DRACR,
135 MISCREG_IRACR,
136 MISCREG_RGNR,
137 MISCREG_BPIALLIS,
138 MISCREG_BPIALL,
139 MISCREG_BPIMVA,
140 MISCREG_DCIMVAC,
141 MISCREG_DCISW,
141 MISCREG_DCCMVAC,
142 MISCREG_MCCSW,
143 MISCREG_DCCMVAU,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices
148 MISCREG_NOP = MISCREG_CP15_END,
149 MISCREG_RAZ,
150
151 NUM_MISCREGS
152 };
153
154 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
142 MISCREG_MCCSW,
143 MISCREG_DCCMVAU,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices
148 MISCREG_NOP = MISCREG_CP15_END,
149 MISCREG_RAZ,
150
151 NUM_MISCREGS
152 };
153
154 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "dccisw", "dccimvac",
161 "sctlr", "dccisw", "dccimvac", "dccmvac",
162 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
163 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
164 "icialluis", "iciallu", "icimvau",
165 "ctr", "tcmtr", "mpuir", "mpidr", "midr",
166 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
167 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
168 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
169 "ccsidr", "aidr", "csselr", "actlr",
170 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
171 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
172 "rgnr", "bpiallis",
162 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
163 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
164 "icialluis", "iciallu", "icimvau",
165 "ctr", "tcmtr", "mpuir", "mpidr", "midr",
166 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
167 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
168 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
169 "ccsidr", "aidr", "csselr", "actlr",
170 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
171 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
172 "rgnr", "bpiallis",
173 "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
173 "bpiall", "bpimva", "dcimvac", "dcisw", "mccsw",
174 "dccmvau",
175 "nop", "raz"
176 };
177
178 BitUnion32(CPSR)
179 Bitfield<31> n;
180 Bitfield<30> z;
181 Bitfield<29> c;

--- 52 unchanged lines hidden --- 		174 "dccmvau",
175 "nop", "raz"
176 };
177
178 BitUnion32(CPSR)
179 Bitfield<31> n;
180 Bitfield<30> z;
181 Bitfield<29> c;

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