miscregs.hh (7267:fcbf902646a8) miscregs.hh (7268:22f75f96c56c)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
86 MISCREG_DCCIMVAC,
87 MISCREG_CONTEXTIDR,
88 MISCREG_TPIDRURW,
89 MISCREG_TPIDRURO,
90 MISCREG_TPIDRPRW,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
86 MISCREG_DCCIMVAC,
87 MISCREG_CONTEXTIDR,
88 MISCREG_TPIDRURW,
89 MISCREG_TPIDRURO,
90 MISCREG_TPIDRPRW,
91 MISCREG_CP15ISB,
91 MISCREG_CP15_UNIMP_START,
92 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
93 MISCREG_TCMTR,
94 MISCREG_MPUIR,
95 MISCREG_MPIDR,
96 MISCREG_MIDR,
97 MISCREG_ID_PFR0,
98 MISCREG_ID_PFR1,

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126 MISCREG_IRSR,
127 MISCREG_DRACR,
128 MISCREG_IRACR,
129 MISCREG_RGNR,
130 MISCREG_ICIALLUIS,
131 MISCREG_BPIALLIS,
132 MISCREG_ICIALLU,
133 MISCREG_ICIMVAU,
92 MISCREG_CP15_UNIMP_START,
93 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
94 MISCREG_TCMTR,
95 MISCREG_MPUIR,
96 MISCREG_MPIDR,
97 MISCREG_MIDR,
98 MISCREG_ID_PFR0,
99 MISCREG_ID_PFR1,

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127 MISCREG_IRSR,
128 MISCREG_DRACR,
129 MISCREG_IRACR,
130 MISCREG_RGNR,
131 MISCREG_ICIALLUIS,
132 MISCREG_BPIALLIS,
133 MISCREG_ICIALLU,
134 MISCREG_ICIMVAU,
134 MISCREG_CP15ISB,
135 MISCREG_BPIALL,
136 MISCREG_BPIMVA,
137 MISCREG_DCIMVAC,
138 MISCREG_DCISW,
139 MISCREG_DCCMVAC,
140 MISCREG_MCCSW,
141 MISCREG_CP15DSB,
142 MISCREG_CP15DMB,

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155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "dccisw", "dccimvac",
162 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
135 MISCREG_BPIALL,
136 MISCREG_BPIMVA,
137 MISCREG_DCIMVAC,
138 MISCREG_DCISW,
139 MISCREG_DCCMVAC,
140 MISCREG_MCCSW,
141 MISCREG_CP15DSB,
142 MISCREG_CP15DMB,

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155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "dccisw", "dccimvac",
162 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
163 "ctr", "tcmtr", "mpuir", "mpidr", "midr",
163 "cp15isb", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
164 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
165 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
166 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
167 "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
168 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
169 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
170 "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
164 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
165 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
166 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
167 "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
168 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
169 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
170 "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
171 "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
171 "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
172 "cp15dsb", "cp15dmb", "dccmvau",
173 "nop", "raz"
174 };
175
176 BitUnion32(CPSR)
177 Bitfield<31> n;
178 Bitfield<30> z;
179 Bitfield<29> c;

--- 52 unchanged lines hidden --- 		172 "cp15dsb", "cp15dmb", "dccmvau",
173 "nop", "raz"
174 };
175
176 BitUnion32(CPSR)
177 Bitfield<31> n;
178 Bitfield<30> z;
179 Bitfield<29> c;

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