miscregs.hh (7266:362277070cbc) miscregs.hh (7267:fcbf902646a8)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81
82 // CP15 registers
83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 69 unchanged lines hidden (view full) ---

78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81
82 // CP15 registers
83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
86 MISCREG_DCCIMVAC,
86 MISCREG_CONTEXTIDR,
87 MISCREG_TPIDRURW,
88 MISCREG_TPIDRURO,
89 MISCREG_TPIDRPRW,
90 MISCREG_CP15_UNIMP_START,
91 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
92 MISCREG_TCMTR,
93 MISCREG_MPUIR,

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135 MISCREG_BPIMVA,
136 MISCREG_DCIMVAC,
137 MISCREG_DCISW,
138 MISCREG_DCCMVAC,
139 MISCREG_MCCSW,
140 MISCREG_CP15DSB,
141 MISCREG_CP15DMB,
142 MISCREG_DCCMVAU,
87 MISCREG_CONTEXTIDR,
88 MISCREG_TPIDRURW,
89 MISCREG_TPIDRURO,
90 MISCREG_TPIDRPRW,
91 MISCREG_CP15_UNIMP_START,
92 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
93 MISCREG_TCMTR,
94 MISCREG_MPUIR,

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136 MISCREG_BPIMVA,
137 MISCREG_DCIMVAC,
138 MISCREG_DCISW,
139 MISCREG_DCCMVAC,
140 MISCREG_MCCSW,
141 MISCREG_CP15DSB,
142 MISCREG_CP15DMB,
143 MISCREG_DCCMVAU,
143 MISCREG_DCCIMVAC,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices
148 MISCREG_NOP = MISCREG_CP15_END,
149 MISCREG_RAZ,
150
151 NUM_MISCREGS
152 };
153
154 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
144
145 MISCREG_CP15_END,
146
147 // Dummy indices
148 MISCREG_NOP = MISCREG_CP15_END,
149 MISCREG_RAZ,
150
151 NUM_MISCREGS
152 };
153
154 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "dccisw", "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
161 "sctlr", "dccisw", "dccimvac",
162 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
162 "ctr", "tcmtr", "mpuir", "mpidr", "midr",
163 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
164 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
165 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
166 "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
167 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
168 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
169 "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
170 "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
163 "ctr", "tcmtr", "mpuir", "mpidr", "midr",
164 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
165 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
166 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
167 "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
168 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
169 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
170 "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
171 "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
171 "cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
172 "cp15dsb", "cp15dmb", "dccmvau",
172 "nop", "raz"
173 };
174
175 BitUnion32(CPSR)
176 Bitfield<31> n;
177 Bitfield<30> z;
178 Bitfield<29> c;
179 Bitfield<28> v;

--- 51 unchanged lines hidden --- 		173 "nop", "raz"
174 };
175
176 BitUnion32(CPSR)
177 Bitfield<31> n;
178 Bitfield<30> z;
179 Bitfield<29> c;
180 Bitfield<28> v;

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