miscregs.hh (7264:fc3dfbfb3066) miscregs.hh (7265:24af07cbec8c)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81
82 // CP15 registers
83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81
82 // CP15 registers
83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
86 MISCREG_CONTEXTIDR,
86 MISCREG_CP15_UNIMP_START,
87 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
88 MISCREG_TCMTR,
89 MISCREG_MPUIR,
90 MISCREG_MPIDR,
91 MISCREG_MIDR,
92 MISCREG_ID_PFR0,
93 MISCREG_ID_PFR1,

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132 MISCREG_DCIMVAC,
133 MISCREG_DCISW,
134 MISCREG_DCCMVAC,
135 MISCREG_MCCSW,
136 MISCREG_CP15DSB,
137 MISCREG_CP15DMB,
138 MISCREG_DCCMVAU,
139 MISCREG_DCCIMVAC,
87 MISCREG_CP15_UNIMP_START,
88 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
89 MISCREG_TCMTR,
90 MISCREG_MPUIR,
91 MISCREG_MPIDR,
92 MISCREG_MIDR,
93 MISCREG_ID_PFR0,
94 MISCREG_ID_PFR1,

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133 MISCREG_DCIMVAC,
134 MISCREG_DCISW,
135 MISCREG_DCCMVAC,
136 MISCREG_MCCSW,
137 MISCREG_CP15DSB,
138 MISCREG_CP15DMB,
139 MISCREG_DCCMVAU,
140 MISCREG_DCCIMVAC,
140 MISCREG_CONTEXTIDR,
141 MISCREG_TPIDRURW,
142 MISCREG_TPIDRURO,
143 MISCREG_TPIDRPRW,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices
148 MISCREG_NOP = MISCREG_CP15_END,

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153
154 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
141 MISCREG_TPIDRURW,
142 MISCREG_TPIDRURO,
143 MISCREG_TPIDRPRW,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices
148 MISCREG_NOP = MISCREG_CP15_END,

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153
154 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "dccisw", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
161 "sctlr", "dccisw", "contextidr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
162 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
163 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
164 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
165 "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
166 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
167 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
168 "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
169 "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
170 "cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
162 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
163 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
164 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
165 "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
166 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
167 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
168 "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
169 "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
170 "cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
171 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
171 "tpidrurw", "tpidruro", "tpidrprw",
172 "nop", "raz"
173 };
174
175 BitUnion32(CPSR)
176 Bitfield<31> n;
177 Bitfield<30> z;
178 Bitfield<29> c;
179 Bitfield<28> v;

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173 };
174
175 BitUnion32(CPSR)
176 Bitfield<31> n;
177 Bitfield<30> z;
178 Bitfield<29> c;
179 Bitfield<28> v;

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