miscregs.hh (7111:ee902ae075bb) miscregs.hh (7259:200840489735)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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73 MISCREG_SPSR_SVC,
74 MISCREG_SPSR_MON,
75 MISCREG_SPSR_UND,
76 MISCREG_SPSR_ABT,
77 MISCREG_FPSR,
78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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73 MISCREG_SPSR_SVC,
74 MISCREG_SPSR_MON,
75 MISCREG_SPSR_UND,
76 MISCREG_SPSR_ABT,
77 MISCREG_FPSR,
78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81 MISCREG_SCTLR,
81
82 // CP15 registers
83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_CP15_UNIMP_START,
86 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
87 MISCREG_TCMTR,
88 MISCREG_MPUIR,
89 MISCREG_MPIDR,
90 MISCREG_MIDR,
91 MISCREG_ID_PFR0,
92 MISCREG_ID_PFR1,
93 MISCREG_ID_DFR0,
94 MISCREG_ID_AFR0,
95 MISCREG_ID_MMFR0,
96 MISCREG_ID_MMFR1,
97 MISCREG_ID_MMFR2,
98 MISCREG_ID_MMFR3,
99 MISCREG_ID_ISAR0,
100 MISCREG_ID_ISAR1,
101 MISCREG_ID_ISAR2,
102 MISCREG_ID_ISAR3,
103 MISCREG_ID_ISAR4,
104 MISCREG_ID_ISAR5,
105 MISCREG_CCSIDR,
106 MISCREG_CLIDR,
107 MISCREG_AIDR,
108 MISCREG_CSSELR,
109 MISCREG_ACTLR,
110 MISCREG_CPACR,
111 MISCREG_DFSR,
112 MISCREG_IFSR,
113 MISCREG_ADFSR,
114 MISCREG_AIFSR,
115 MISCREG_DFAR,
116 MISCREG_IFAR,
117 MISCREG_DRBAR,
118 MISCREG_IRBAR,
119 MISCREG_DRSR,
120 MISCREG_IRSR,
121 MISCREG_DRACR,
122 MISCREG_IRACR,
123 MISCREG_RGNR,
124 MISCREG_ICIALLUIS,
125 MISCREG_BPIALLIS,
126 MISCREG_ICIALLU,
127 MISCREG_ICIMVAU,
128 MISCREG_CP15ISB,
129 MISCREG_BPIALL,
130 MISCREG_BPIMVA,
131 MISCREG_DCIMVAC,
132 MISCREG_DCISW,
133 MISCREG_DCCMVAC,
134 MISCREG_MCCSW,
135 MISCREG_CP15DSB,
136 MISCREG_CP15DMB,
137 MISCREG_DCCMVAU,
138 MISCREG_DCCIMVAC,
139 MISCREG_DCCISW,
140 MISCREG_CONTEXTIDR,
141 MISCREG_TPIDRURW,
142 MISCREG_TPIDRURO,
143 MISCREG_TPIDRPRW,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices
148 MISCREG_NOP = MISCREG_CP15_END,
149 MISCREG_RAZ,
150
82 NUM_MISCREGS
83 };
84
151 NUM_MISCREGS
152 };
153
154 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
155 unsigned crm, unsigned opc2);
156
85 const char * const miscRegName[NUM_MISCREGS] = {
157 const char * const miscRegName[NUM_MISCREGS] = {
86 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
87 "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
162 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
163 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
164 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
165 "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
166 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
167 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
168 "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
169 "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
170 "cp15dsb", "cp15dmb", "dccmvau", "dccimvac", "dccisw",
171 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
172 "nop", "raz"
88 };
89
90 BitUnion32(CPSR)
91 Bitfield<31> n;
92 Bitfield<30> z;
93 Bitfield<29> c;
94 Bitfield<28> v;
95 Bitfield<27> q;

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174
175 BitUnion32(CPSR)
176 Bitfield<31> n;
177 Bitfield<30> z;
178 Bitfield<29> c;
179 Bitfield<28> v;
180 Bitfield<27> q;

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