miscregs.hh (6723:ea7c71a3433a) miscregs.hh (6735:6437ad24a8a0)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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50 COND_GT, // 12
51 COND_LE, // 13
52 COND_AL, // 14
53 COND_NV // 15
54 };
55
56 enum MiscRegIndex {
57 MISCREG_CPSR = 0,
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 41 unchanged lines hidden (view full) ---

50 COND_GT, // 12
51 COND_LE, // 13
52 COND_AL, // 14
53 COND_NV // 15
54 };
55
56 enum MiscRegIndex {
57 MISCREG_CPSR = 0,
58 MISCREG_SPSR,
58 MISCREG_SPSR,
59 MISCREG_SPSR_FIQ,
60 MISCREG_SPSR_IRQ,
61 MISCREG_SPSR_SVC,
62 MISCREG_SPSR_MON,
63 MISCREG_SPSR_UND,
64 MISCREG_SPSR_ABT,
65 MISCREG_FPSR,
66 MISCREG_FPSID,
67 MISCREG_FPSCR,
68 MISCREG_FPEXC,
59 MISCREG_SPSR_FIQ,
60 MISCREG_SPSR_IRQ,
61 MISCREG_SPSR_SVC,
62 MISCREG_SPSR_MON,
63 MISCREG_SPSR_UND,
64 MISCREG_SPSR_ABT,
65 MISCREG_FPSR,
66 MISCREG_FPSID,
67 MISCREG_FPSCR,
68 MISCREG_FPEXC,
69 NUM_MISCREGS
69 MISCREG_SCTLR,
70 NUM_MISCREGS
70 };
71
72 const char * const miscRegName[NUM_MISCREGS] = {
71 };
72
73 const char * const miscRegName[NUM_MISCREGS] = {
73 "cpsr",
74 "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", "spsr_abt",
75 "fpsr"
74 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
75 "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
76 };
77
78 BitUnion32(CPSR)
79 Bitfield<31> n;
80 Bitfield<30> z;
81 Bitfield<29> c;
82 Bitfield<28> v;
83 Bitfield<27> q;
76 };
77
78 BitUnion32(CPSR)
79 Bitfield<31> n;
80 Bitfield<30> z;
81 Bitfield<29> c;
82 Bitfield<28> v;
83 Bitfield<27> q;
84 Bitfield<26,25> it1;
84 Bitfield<24> j;
85 Bitfield<19, 16> ge;
85 Bitfield<24> j;
86 Bitfield<19, 16> ge;
87 Bitfield<15,10> it2;
86 Bitfield<9> e;
87 Bitfield<8> a;
88 Bitfield<7> i;
89 Bitfield<6> f;
90 Bitfield<5> t;
91 Bitfield<4, 0> mode;
92 EndBitUnion(CPSR)
88 Bitfield<9> e;
89 Bitfield<8> a;
90 Bitfield<7> i;
91 Bitfield<6> f;
92 Bitfield<5> t;
93 Bitfield<4, 0> mode;
94 EndBitUnion(CPSR)
95
96 BitUnion32(SCTLR)
97 Bitfield<30> te; // Thumb Exception Enable
98 Bitfield<29> afe; // Access flag enable
99 Bitfield<28> tre; // TEX Remap bit
100 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
101 Bitfield<25> ee; // Exception Endianness bit
102 Bitfield<24> ve; // Interrupt vectors enable
103 Bitfield<23> rao1;// Read as one
104 Bitfield<22> u; // Alignment (now unused)
105 Bitfield<21> fi; // Fast interrupts configuration enable
106 Bitfield<18> rao2;// Read as one
107 Bitfield<17> ha; // Hardware access flag enable
108 Bitfield<16> rao3;// Read as one
109 Bitfield<14> rr; // Round robin cache replacement
110 Bitfield<13> v; // Base address for exception vectors
111 Bitfield<12> i; // instruction cache enable
112 Bitfield<11> z; // branch prediction enable bit
113 Bitfield<10> sw; // Enable swp/swpb
114 Bitfield<6,3> rao4;// Read as one
115 Bitfield<7> b; // Endianness support (unused)
116 Bitfield<2> c; // Cache enable bit
117 Bitfield<1> a; // Alignment fault checking
118 Bitfield<0> m; // MMU enable bit
119 EndBitUnion(SCTLR)
93};
94
95#endif // __ARCH_ARM_MISCREGS_HH__
120};
121
122#endif // __ARCH_ARM_MISCREGS_HH__