miscregs.hh (6242:1cee707c1228) miscregs.hh (6261:5fdf0fc147bd)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 41 unchanged lines hidden (view full) ---

50 COND_GT, // 12
51 COND_LE, // 13
52 COND_AL, // 14
53 COND_NV // 15
54 };
55
56 enum MiscRegIndex {
57 MISCREG_CPSR = 0,
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 41 unchanged lines hidden (view full) ---

50 COND_GT, // 12
51 COND_LE, // 13
52 COND_AL, // 14
53 COND_NV // 15
54 };
55
56 enum MiscRegIndex {
57 MISCREG_CPSR = 0,
58 MISCREG_SPSR,
58 MISCREG_SPSR_FIQ,
59 MISCREG_SPSR_IRQ,
60 MISCREG_SPSR_SVC,
61 MISCREG_SPSR_UND,
62 MISCREG_SPSR_ABT,
59 MISCREG_SPSR_FIQ,
60 MISCREG_SPSR_IRQ,
61 MISCREG_SPSR_SVC,
62 MISCREG_SPSR_UND,
63 MISCREG_SPSR_ABT,
63 MISCREG_FPSR
64 MISCREG_FPSR,
65 NUM_MISCREGS
64 };
65
66 };
67
68 const char * const miscRegName[NUM_MISCREGS] = {
69 "cpsr",
70 "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", "spsr_abt",
71 "fpsr"
72 };
73
66 BitUnion32(CPSR)
67 Bitfield<31> n;
68 Bitfield<30> z;
69 Bitfield<29> c;
70 Bitfield<28> v;
71 Bitfield<27> q;
72 Bitfield<24> j;
73 Bitfield<19, 16> ge;
74 Bitfield<9> e;
75 Bitfield<8> a;
76 Bitfield<7> i;
77 Bitfield<6> f;
78 Bitfield<5> t;
79 Bitfield<4, 0> mode;
80 EndBitUnion(CPSR)
81};
82
83#endif // __ARCH_ARM_MISCREGS_HH__
74 BitUnion32(CPSR)
75 Bitfield<31> n;
76 Bitfield<30> z;
77 Bitfield<29> c;
78 Bitfield<28> v;
79 Bitfield<27> q;
80 Bitfield<24> j;
81 Bitfield<19, 16> ge;
82 Bitfield<9> e;
83 Bitfield<8> a;
84 Bitfield<7> i;
85 Bitfield<6> f;
86 Bitfield<5> t;
87 Bitfield<4, 0> mode;
88 EndBitUnion(CPSR)
89};
90
91#endif // __ARCH_ARM_MISCREGS_HH__